commit c429aabb916fbf951abcb1c091239db642ccb233
author Andre Vieira <andre.simoesdiasvieira@arm.com> Mon Sep 11 11:11:17 2017 +0000
committer Andre Vieira <andre.simoesdiasvieira@arm.com> Mon Sep 11 11:11:17 2017 +0000
tree 140cf4cd82e0060d28ad05b2c3cd36aa0dee8073
parent 9707ba09570740288416dd187eece06375ac79c3

[ARM] Enable the use of SVC anywhere in an IT block

Differential Revision: https://reviews.llvm.org/D37374

llvm-svn: 312908

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 5e5931d..43135ad 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8717,9 +8717,10 @@
 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
 
-  // All branch & call instructions terminate IT blocks.
-  if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() ||
-      MCID.isBranch() || MCID.isIndirectBranch())
+  // All branch & call instructions terminate IT blocks with the exception of
+  // SVC.
+  if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
+      MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
     return true;
 
   // Any arithmetic instruction which writes to the PC also terminates the IT