commit c507cdb4bca79c6a82061c114c1d0d6e6eee73a1
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Nov 01 23:22:17 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Nov 01 23:22:17 2016 +0000
tree 33c54c998dd010085ed3479694698654d31b1ced
parent 0f1767ddce60cbe3c63cb52c9e7ec820972b2dfe

AMDGPU: Handle CopyToReg in getOperandRegClass

llvm-svn: 285768

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index b035c87..2b3b3fd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -183,8 +183,21 @@
 /// determined.
 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
                                                           unsigned OpNo) const {
-  if (!N->isMachineOpcode())
+  if (!N->isMachineOpcode()) {
+    if (N->getOpcode() == ISD::CopyToReg) {
+      unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
+      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
+        MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
+        return MRI.getRegClass(Reg);
+      }
+
+      const SIRegisterInfo *TRI
+        = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo();
+      return TRI->getPhysRegClass(Reg);
+    }
+
     return nullptr;
+  }
 
   switch (N->getMachineOpcode()) {
   default: {