[X86FixupBWInsts] Fix miscompilation if sibling sub-register is live.
Summary: The issues was found during D40524.
Reviewers: andrew.w.kaylor, craig.topper, MatzeB
Reviewed By: andrew.w.kaylor
Subscribers: aivchenk, llvm-commits
Differential Revision: https://reviews.llvm.org/D42533
llvm-svn: 323635
diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
index 855ea68..9a2f172 100644
--- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp
+++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
@@ -249,15 +249,16 @@
assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
- for (MCSuperRegIterator Supers(OrigDestReg, TRI, true); Supers.isValid();
- ++Supers) {
- if (*Supers == MO.getReg()) {
- if (MO.isDef())
- IsDefined = true;
- else
- return false; // SuperReg Imp-used' -> live before the MI
- }
- }
+ if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
+ IsDefined = true;
+
+ // If MO is a use of any part of the destination register but is not equal
+ // to OrigDestReg or one of its subregisters, we cannot use SuperDestReg.
+ // For example, if OrigDestReg is %al then an implicit use of %ah, %ax,
+ // %eax, or %rax will prevent us from using the %eax register.
+ if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
+ TRI->regsOverlap(SuperDestReg, MO.getReg()))
+ return false;
}
// Reg is not Imp-def'ed -> it's live both before/after the instruction.
if (!IsDefined)