[SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.
llvm-svn: 186686
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll
index 04813f9..6a919a72 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll
@@ -1,6 +1,6 @@
; Test 32-bit atomic additions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll
index f3814f2..3b5c0d0 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll
@@ -1,6 +1,6 @@
; Test 64-bit atomic additions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check addition of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
index b0c1769..64ec603 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
@@ -1,6 +1,6 @@
; Test 32-bit atomic subtractions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check subtraction of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
index c0fd9f9..18929b8 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
@@ -1,6 +1,6 @@
; Test 64-bit atomic subtractions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check subtraction of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/int-add-02.ll b/llvm/test/CodeGen/SystemZ/int-add-02.ll
index 0d4c8ce..4386b5a 100644
--- a/llvm/test/CodeGen/SystemZ/int-add-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-add-02.ll
@@ -1,6 +1,7 @@
; Test 32-bit addition in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/int-add-05.ll b/llvm/test/CodeGen/SystemZ/int-add-05.ll
index 4f39a2d..a05fdd9 100644
--- a/llvm/test/CodeGen/SystemZ/int-add-05.ll
+++ b/llvm/test/CodeGen/SystemZ/int-add-05.ll
@@ -1,6 +1,7 @@
; Test 64-bit addition in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/int-add-13.ll b/llvm/test/CodeGen/SystemZ/int-add-13.ll
new file mode 100644
index 0000000..7dfabbc
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-add-13.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of addition.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check ARK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: ark %r2, %r3, %r4
+; CHECK: br %r14
+ %add = add i32 %b, %c
+ ret i32 %add
+}
+
+; Check that we can still use AR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: ar %r2, %r3
+; CHECK: br %r14
+ %add = add i32 %a, %b
+ ret i32 %add
+}
+
+; Check AGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: agrk %r2, %r3, %r4
+; CHECK: br %r14
+ %add = add i64 %b, %c
+ ret i64 %add
+}
+
+; Check that we can still use AGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: agr %r2, %r3
+; CHECK: br %r14
+ %add = add i64 %a, %b
+ ret i64 %add
+}
diff --git a/llvm/test/CodeGen/SystemZ/int-sub-01.ll b/llvm/test/CodeGen/SystemZ/int-sub-01.ll
index ac3a5ff..8d1e56d 100644
--- a/llvm/test/CodeGen/SystemZ/int-sub-01.ll
+++ b/llvm/test/CodeGen/SystemZ/int-sub-01.ll
@@ -1,6 +1,7 @@
; Test 32-bit subtraction.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/int-sub-04.ll b/llvm/test/CodeGen/SystemZ/int-sub-04.ll
index 9547756..8510453 100644
--- a/llvm/test/CodeGen/SystemZ/int-sub-04.ll
+++ b/llvm/test/CodeGen/SystemZ/int-sub-04.ll
@@ -1,6 +1,7 @@
; Test 64-bit subtraction in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/int-sub-08.ll b/llvm/test/CodeGen/SystemZ/int-sub-08.ll
new file mode 100644
index 0000000..f0a5e1e
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-sub-08.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of subtraction.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check SRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: srk %r2, %r3, %r4
+; CHECK: br %r14
+ %sub = sub i32 %b, %c
+ ret i32 %sub
+}
+
+; Check that we can still use SR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: sr %r2, %r3
+; CHECK: br %r14
+ %sub = sub i32 %a, %b
+ ret i32 %sub
+}
+
+; Check SGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: sgrk %r2, %r3, %r4
+; CHECK: br %r14
+ %sub = sub i64 %b, %c
+ ret i64 %sub
+}
+
+; Check that we can still use SGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: sgr %r2, %r3
+; CHECK: br %r14
+ %sub = sub i64 %a, %b
+ ret i64 %sub
+}