ARMFrameLowering: Only set ExtraCSSpill for actually unused registers.
The code assumed that unclobbered/unspilled callee saved registers are
unused in the function. This is not true for callee saved registers that are
also used to pass parameters such as swiftself.
rdar://33401922
llvm-svn: 309350
diff --git a/llvm/test/CodeGen/ARM/pei-swiftself.mir b/llvm/test/CodeGen/ARM/pei-swiftself.mir
new file mode 100644
index 0000000..055efee
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/pei-swiftself.mir
@@ -0,0 +1,60 @@
+# RUN: llc -o - %s -mtriple=arm-- -run-pass prologepilog | FileCheck %s
+--- |
+ define swiftcc i8* @need_emergency_slot(i8 *swiftself %v) {
+ ; Just a dummy to add a swiftself bit. The real code is in the MI below.
+ unreachable
+ }
+...
+---
+# CHECK-LABEL: name: need_emergency_slot
+# Make sure we do not just assume an unsaved/restored callee saved register
+# is free to use. Callee saved parameters may still be used if they were used
+# to pass arguments (as in swiftself).
+name: need_emergency_slot
+tracksRegLiveness: true
+stack:
+ - { id: 0, type: default, size: 8, alignment: 8 }
+ - { id: 1, type: default, size: 4096, alignment: 8 }
+body: |
+ bb.0:
+ liveins: %r10 ; swiftself parameter comes in as %r10
+
+ ; Bring up register pressure to force emergency spilling, coax scavenging
+ ; to use %r10 as that one is not spilled/restored.
+ %r0 = IMPLICIT_DEF
+ %r1 = IMPLICIT_DEF
+ %r2 = IMPLICIT_DEF
+ %r3 = IMPLICIT_DEF
+ %r4 = IMPLICIT_DEF
+ %r5 = IMPLICIT_DEF
+ %r6 = IMPLICIT_DEF
+ %r7 = IMPLICIT_DEF
+ %r8 = IMPLICIT_DEF
+ %r9 = IMPLICIT_DEF
+ %r11 = IMPLICIT_DEF
+ %r12 = IMPLICIT_DEF
+ %lr = IMPLICIT_DEF
+
+ ; Computing the large stack offset requires an extra register. We should
+ ; not just use %r10 for that.
+ ; CHECK-NOT: STRi12 %1,{{.*}}%r10
+
+ STRi12 %r1, %stack.0, 0, 14, _ :: (store 4)
+
+ ; use the swiftself parameter value.
+ KILL %r10
+
+ KILL %r0
+ KILL %r1
+ KILL %r2
+ KILL %r3
+ KILL %r4
+ KILL %r5
+ KILL %r6
+ KILL %r7
+ KILL %r8
+ KILL %r9
+ KILL %r11
+ KILL %r12
+ KILL %lr
+...