LivePhysRegs/IfConversion: Change some types from unsigned to MCPhysReg; NFC
Change the type in a couple of lists and sets that only store physical
registers from unsigned to MCPhysRegs. The later is only 16bits and
saves us a bit of memory.
llvm-svn: 346254
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index f12d000..5666626 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -273,7 +273,7 @@
void PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,
- SmallSet<unsigned, 4> *LaterRedefs = nullptr);
+ SmallSet<MCPhysReg, 4> *LaterRedefs = nullptr);
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
SmallVectorImpl<MachineOperand> &Cond,
bool IgnoreBr = false);
@@ -1366,12 +1366,12 @@
// Before stepping forward past MI, remember which regs were live
// before MI. This is needed to set the Undef flag only when reg is
// dead.
- SparseSet<unsigned> LiveBeforeMI;
+ SparseSet<MCPhysReg, identity<MCPhysReg>> LiveBeforeMI;
LiveBeforeMI.setUniverse(TRI->getNumRegs());
for (unsigned Reg : Redefs)
LiveBeforeMI.insert(Reg);
- SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
+ SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Clobbers;
Redefs.stepForward(MI, Clobbers);
// Now add the implicit uses for each of the clobbered values.
@@ -1740,7 +1740,7 @@
if (MRI->tracksLiveness()) {
for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) {
- SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Dummy;
+ SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Dummy;
Redefs.stepForward(MI, Dummy);
}
}
@@ -1806,13 +1806,13 @@
// generate:
// sub r0, r1, #1
// addne r0, r1, #1
- SmallSet<unsigned, 4> RedefsByFalse;
- SmallSet<unsigned, 4> ExtUses;
+ SmallSet<MCPhysReg, 4> RedefsByFalse;
+ SmallSet<MCPhysReg, 4> ExtUses;
if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {
for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
if (FI.isDebugInstr())
continue;
- SmallVector<unsigned, 4> Defs;
+ SmallVector<MCPhysReg, 4> Defs;
for (const MachineOperand &MO : FI.operands()) {
if (!MO.isReg())
continue;
@@ -1830,7 +1830,7 @@
}
}
- for (unsigned Reg : Defs) {
+ for (MCPhysReg Reg : Defs) {
if (!ExtUses.count(Reg)) {
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
@@ -1976,7 +1976,7 @@
}
static bool MaySpeculate(const MachineInstr &MI,
- SmallSet<unsigned, 4> &LaterRedefs) {
+ SmallSet<MCPhysReg, 4> &LaterRedefs) {
bool SawStore = true;
if (!MI.isSafeToMove(nullptr, SawStore))
return false;
@@ -1999,7 +1999,7 @@
void IfConverter::PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,
- SmallSet<unsigned, 4> *LaterRedefs) {
+ SmallSet<MCPhysReg, 4> *LaterRedefs) {
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;
for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {