commit c86e0f38739eef5302e2c5d9dea16f4c4dca3134
author Venkatraman Govindaraju <venkatra@cs.wisc.edu> Sat Mar 01 22:03:07 2014 +0000
committer Venkatraman Govindaraju <venkatra@cs.wisc.edu> Sat Mar 01 22:03:07 2014 +0000
tree ed0ab474e7b81e8fd24d75e125c973496b6467fe
parent 2430958182b84df0ebcb502e02bd6978cfecc55c

[SparcV9] Add support for parsing branch instructions with prediction.

llvm-svn: 202602

llvm/lib/Target/Sparc/SparcCodeEmitter.cpp

diff --git a/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp b/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
index b7b2182..6b5e4bf 100644
--- a/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
+++ b/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
@@ -76,6 +76,8 @@
                                 unsigned) const;
   unsigned getBranchTargetOpValue(const MachineInstr &MI,
                                   unsigned) const;
+  unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
+                                      unsigned) const;
 
   void emitWord(unsigned Word);
 
@@ -198,6 +200,12 @@
   return getMachineOpValue(MI, MO);
 }
 
+unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI,
+                                                      unsigned opIdx) const {
+  const MachineOperand MO = MI.getOperand(opIdx);
+  return getMachineOpValue(MI, MO);
+}
+
 unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
                                          const MachineOperand &MO) const {