commit c88b7ecb88267be1c53ec7a56352db3ffb572210
author Andrew Trick <atrick@apple.com> Fri Mar 04 02:03:45 2011 +0000
committer Andrew Trick <atrick@apple.com> Fri Mar 04 02:03:45 2011 +0000
tree bb603b64fb2d12a3546185022569737cf4bfeedb
parent 60a084a24df235d9960b77e7e2bc78745ea97d31

Minor pre-RA-sched fixes and cleanup.
Fix the PendingQueue, then disable it because it's not required for
the current schedulers' heuristics.
Fix the logic for the unused list-ilp scheduler.

llvm-svn: 126981

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 0b548b2..d253b31 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -295,7 +295,7 @@
     if (Height < MinAvailableCycle)
       MinAvailableCycle = Height;
 
-    if (isReady(SU)) {
+    if (isReady(PredSU)) {
       AvailableQueue->push(PredSU);
     }
     // CapturePred and others may have left the node in the pending queue, avoid
@@ -502,6 +502,12 @@
 
   AvailableQueue->ScheduledNode(SU);
 
+  // If HazardRec is disabled, count each inst as one cycle.
+  // Advance CurCycle before ReleasePredecessors to avoid useles pushed to
+  // PendingQueue for schedulers that implement HasReadyFilter.
+  if (!HazardRec->isEnabled())
+    AdvanceToCycle(CurCycle + 1);
+
   // Update liveness of predecessors before successors to avoid treating a
   // two-address node as a live range def.
   ReleasePredecessors(SU);
@@ -524,8 +530,10 @@
   // (1) No available instructions
   // (2) All pipelines full, so available instructions must have hazards.
   //
-  // If HazardRec is disabled, count each inst as one cycle.
-  if (!HazardRec->isEnabled() || HazardRec->atIssueLimit()
+  // If HazardRec is disabled, the cycle was advanced earlier.
+  //
+  // Check AvailableQueue after ReleasePredecessors in case of zero latency.
+  if ((HazardRec->isEnabled() && HazardRec->atIssueLimit())
       || AvailableQueue->empty())
     AdvanceToCycle(CurCycle + 1);
 }
@@ -1318,7 +1326,7 @@
 struct hybrid_ls_rr_sort : public queue_sort {
   enum {
     IsBottomUp = true,
-    HasReadyFilter = true
+    HasReadyFilter = false
   };
 
   RegReductionPQBase *SPQ;
@@ -1337,7 +1345,7 @@
 struct ilp_ls_rr_sort : public queue_sort {
   enum {
     IsBottomUp = true,
-    HasReadyFilter = true
+    HasReadyFilter = false
   };
 
   RegReductionPQBase *SPQ;
@@ -2112,7 +2120,7 @@
       != ScheduleHazardRecognizer::NoHazard)
     return false;
 
-  return SU->getHeight() <= CurCycle;
+  return true;
 }
 
 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
@@ -2134,7 +2142,7 @@
     if (left->NumPreds > right->NumPreds)
       return false;
     else if (left->NumPreds < right->NumPreds)
-      return false;
+      return true;
   }
 
   return BURRSort(left, right, SPQ);