[SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings.
As a consequence of recent discussions
(http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patch
changes the SystemZ SchedModels so that the IssueWidth is 6, which is the
decoder capacity, and NumMicroOps become the number of decoder slots needed
per instruction.
In addition, the SchedWrite latencies now match the MachineInstructions
def-operand indexes, and ReadAdvances have been added on instructions with
one register operand and one memory operand.
Review: Ulrich Weigand
https://reviews.llvm.org/D47008
llvm-svn: 337538
diff --git a/llvm/test/CodeGen/SystemZ/int-conv-11.ll b/llvm/test/CodeGen/SystemZ/int-conv-11.ll
index cfa0870..8537088 100644
--- a/llvm/test/CodeGen/SystemZ/int-conv-11.ll
+++ b/llvm/test/CodeGen/SystemZ/int-conv-11.ll
@@ -6,7 +6,7 @@
; to use LLC(H) if possible.
define void @f1(i32 *%ptr) {
; CHECK-LABEL: f1:
-; CHECK: llc{{h?}} {{%r[0-9]+}}, 16{{[37]}}(%r15)
+; CHECK: llc{{h?}} {{%r[0-9]+}}, 1{{[67]}}{{[379]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 , i32 *%ptr
%val1 = load volatile i32 , i32 *%ptr
@@ -179,7 +179,7 @@
; Same again with i16, which should use LLH(H).
define void @f2(i32 *%ptr) {
; CHECK-LABEL: f2:
-; CHECK: llh{{h?}} {{%r[0-9]+}}, 16{{[26]}}(%r15)
+; CHECK: llh{{h?}} {{%r[0-9]+}}, 1{{[67]}}{{[268]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 , i32 *%ptr
%val1 = load volatile i32 , i32 *%ptr
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-08.ll b/llvm/test/CodeGen/SystemZ/int-uadd-08.ll
index 5a069db..f168382 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-08.ll
@@ -100,8 +100,8 @@
; CHECK-LABEL: f7:
; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: bler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgnle foo@PLT
+; CHECK: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -121,8 +121,8 @@
; CHECK-LABEL: f8:
; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: bnler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgle foo@PLT
+; CHECK: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-09.ll b/llvm/test/CodeGen/SystemZ/int-uadd-09.ll
index cf59fb2..050c5c2 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-09.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-09.ll
@@ -98,8 +98,8 @@
; CHECK-LABEL: f7:
; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 1
; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: bler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgnle foo@PLT
+; CHECK: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -119,8 +119,8 @@
; CHECK-LABEL: f8:
; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 1
; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: bnler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgle foo@PLT
+; CHECK: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-08.ll b/llvm/test/CodeGen/SystemZ/int-usub-08.ll
index d282404..feee771 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-08.ll
@@ -106,8 +106,8 @@
; CHECK-LABEL: f7:
; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: bnler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgle foo@PLT
+; CHECK: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -127,8 +127,8 @@
; CHECK-LABEL: f8:
; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: bler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgnle foo@PLT
+; CHECK: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-09.ll b/llvm/test/CodeGen/SystemZ/int-usub-09.ll
index ce5fafa..b116428 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-09.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-09.ll
@@ -103,8 +103,8 @@
; CHECK-LABEL: f7:
; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -1
; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: bnler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgle foo@PLT
+; CHECK: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -124,8 +124,8 @@
; CHECK-LABEL: f8:
; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -1
; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: bler %r14
-; CHECK: jg foo@PLT
+; CHECK: jgnle foo@PLT
+; CHECK: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/pr36164.ll b/llvm/test/CodeGen/SystemZ/pr36164.ll
index 0c85009..312961f 100644
--- a/llvm/test/CodeGen/SystemZ/pr36164.ll
+++ b/llvm/test/CodeGen/SystemZ/pr36164.ll
@@ -46,9 +46,9 @@
; CHECK-NEXT: lrl %r13, g_832
; CHECK-NEXT: strl %r0, g_69
; CHECK-NEXT: lrl %r13, g_832
-; CHECK-NEXT: lghi %r13, 24
-; CHECK-NEXT: strl %r2, g_69
-; CHECK-NEXT: ag %r13, 0(%r1)
+; CHECK-DAG: lghi %r13, 24
+; CHECK-DAG: strl %r2, g_69
+; CHECK-DAG: ag %r13, 0(%r1)
; CHECK-NEXT: lrl %r12, g_832
; CHECK-NEXT: strl %r3, g_69
; CHECK-NEXT: lrl %r12, g_832
diff --git a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
index bcdb3b9..8b7184f 100644
--- a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
+++ b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
; Store a <4 x i31> vector.
@@ -81,34 +80,33 @@
; CHECK-NEXT: vlgvf %r1, %v26, 2
; CHECK-NEXT: risbgn %r4, %r3, 0, 129, 62
; CHECK-NEXT: rosbg %r4, %r1, 2, 32, 31
-; CHECK-NEXT: vlgvf %r0, %v26, 3
-; CHECK-NEXT: rosbg %r4, %r0, 33, 63, 0
-; CHECK-NEXT: stc %r0, 30(%r2)
-; CHECK-NEXT: # kill: def $r0l killed $r0l killed $r0d def $r0d
-; CHECK-NEXT: srl %r0, 8
-; CHECK-NEXT: vlgvf %r1, %v24, 1
-; CHECK-NEXT: vlgvf %r14, %v24, 0
-; CHECK-NEXT: sth %r0, 28(%r2)
-; CHECK-NEXT: vlgvf %r0, %v24, 2
-; CHECK-NEXT: risbgn %r5, %r1, 0, 133, 58
-; CHECK-NEXT: rosbg %r5, %r0, 6, 36, 27
-; CHECK-NEXT: sllg %r14, %r14, 25
-; CHECK-NEXT: rosbg %r14, %r1, 39, 63, 58
-; CHECK-NEXT: vlgvf %r0, %v24, 3
-; CHECK-NEXT: rosbg %r5, %r0, 37, 63, 60
-; CHECK-NEXT: sllg %r1, %r14, 8
-; CHECK-NEXT: rosbg %r1, %r5, 56, 63, 8
-; CHECK-NEXT: stg %r1, 0(%r2)
-; CHECK-NEXT: srlg %r1, %r4, 24
-; CHECK-NEXT: st %r1, 24(%r2)
-; CHECK-NEXT: vlgvf %r1, %v26, 0
-; CHECK-NEXT: risbgn %r0, %r0, 0, 131, 60
-; CHECK-NEXT: rosbg %r0, %r1, 4, 34, 29
-; CHECK-NEXT: sllg %r1, %r5, 8
-; CHECK-NEXT: rosbg %r0, %r3, 35, 63, 62
-; CHECK-NEXT: rosbg %r1, %r0, 56, 63, 8
-; CHECK-NEXT: stg %r1, 8(%r2)
-; CHECK-NEXT: sllg %r0, %r0, 8
+; CHECK-DAG: vlgvf %r0, %v26, 3
+; CHECK-DAG: rosbg %r4, %r0, 33, 63, 0
+; CHECK-DAG: stc %r0, 30(%r2)
+; CHECK-DAG: srl %r0, 8
+; CHECK-DAG: vlgvf [[REG0:%r[0-9]+]], %v24, 1
+; CHECK-DAG: vlgvf [[REG1:%r[0-9]+]], %v24, 0
+; CHECK-DAG: sth %r0, 28(%r2)
+; CHECK-DAG: vlgvf [[REG2:%r[0-9]+]], %v24, 2
+; CHECK-DAG: risbgn [[REG3:%r[0-9]+]], [[REG0]], 0, 133, 58
+; CHECK-DAG: rosbg [[REG3]], [[REG2]], 6, 36, 27
+; CHECK-DAG: sllg [[REG4:%r[0-9]+]], [[REG1]], 25
+; CHECK-DAG: rosbg [[REG4]], [[REG0]], 39, 63, 58
+; CHECK-DAG: vlgvf [[REG5:%r[0-9]+]], %v24, 3
+; CHECK-DAG: rosbg [[REG3]], [[REG5]], 37, 63, 60
+; CHECK-DAG: sllg [[REG6:%r[0-9]+]], [[REG4]], 8
+; CHECK-DAG: rosbg [[REG6]], [[REG3]], 56, 63, 8
+; CHECK-NEXT: stg [[REG6]], 0(%r2)
+; CHECK-NEXT: srlg [[REG7:%r[0-9]+]], %r4, 24
+; CHECK-NEXT: st [[REG7]], 24(%r2)
+; CHECK-NEXT: vlgvf [[REG8:%r[0-9]+]], %v26, 0
+; CHECK-NEXT: risbgn [[REG10:%r[0-9]+]], [[REG5]], 0, 131, 60
+; CHECK-NEXT: rosbg [[REG10]], [[REG8]], 4, 34, 29
+; CHECK-NEXT: sllg [[REG9:%r[0-9]+]], [[REG3]], 8
+; CHECK-NEXT: rosbg [[REG10]], %r3, 35, 63, 62
+; CHECK-NEXT: rosbg [[REG9]], [[REG10]], 56, 63, 8
+; CHECK-NEXT: stg [[REG9]], 8(%r2)
+; CHECK-NEXT: sllg %r0, [[REG10]], 8
; CHECK-NEXT: rosbg %r0, %r4, 56, 63, 8
; CHECK-NEXT: stg %r0, 16(%r2)
; CHECK-NEXT: lmg %r14, %r15, 112(%r15)
diff --git a/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll b/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
index ac12861..8714a5a 100644
--- a/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
@@ -457,9 +457,9 @@
; CHECK-NEXT: vceqf [[REG0:%v[0-9]+]], %v25, %v27
; CHECK-NEXT: vuphf [[REG1:%v[0-9]+]], [[REG0]]
; CHECK-NEXT: vmrlg [[REG2:%v[0-9]+]], [[REG0]], [[REG0]]
-; CHECK-NEXT: vceqg [[REG3:%v[0-9]+]], %v24, %v28
-; CHECK-NEXT: vceqg [[REG4:%v[0-9]+]], %v26, %v30
-; CHECK-NEXT: vuphf [[REG5:%v[0-9]+]], [[REG2]]
+; CHECK-DAG: vceqg [[REG3:%v[0-9]+]], %v24, %v28
+; CHECK-DAG: vceqg [[REG4:%v[0-9]+]], %v26, %v30
+; CHECK-DAG: vuphf [[REG5:%v[0-9]+]], [[REG2]]
; CHECK-DAG: vl [[REG6:%v[0-9]+]], 176(%r15)
; CHECK-DAG: vl [[REG7:%v[0-9]+]], 160(%r15)
; CHECK-DAG: vx [[REG8:%v[0-9]+]], [[REG4]], [[REG5]]
@@ -711,14 +711,14 @@
; CHECK-Z14-NEXT: vfchdb %v6, %v25, %v6
; CHECK-Z14-NEXT: vfchdb %v5, %v31, %v5
; CHECK-Z14-NEXT: vfchdb %v4, %v29, %v4
-; CHECK-Z14-NEXT: vfchsb %v16, %v24, %v28
-; CHECK-Z14-NEXT: vfchsb %v17, %v26, %v30
-; CHECK-Z14-NEXT: vpkg %v6, %v6, %v7
-; CHECK-Z14-NEXT: vpkg %v4, %v4, %v5
-; CHECK-Z14-NEXT: vl %v0, 272(%r15)
-; CHECK-Z14-NEXT: vl %v1, 240(%r15)
-; CHECK-Z14-NEXT: vl %v2, 256(%r15)
-; CHECK-Z14-NEXT: vl %v3, 224(%r15)
+; CHECK-Z14-DAG: vfchsb %v16, %v24, %v28
+; CHECK-Z14-DAG: vfchsb %v17, %v26, %v30
+; CHECK-Z14-DAG: vpkg %v6, %v6, %v7
+; CHECK-Z14-DAG: vpkg %v4, %v4, %v5
+; CHECK-Z14-DAG: vl %v0, 272(%r15)
+; CHECK-Z14-DAG: vl %v1, 240(%r15)
+; CHECK-Z14-DAG: vl %v2, 256(%r15)
+; CHECK-Z14-DAG: vl %v3, 224(%r15)
; CHECK-Z14-NEXT: vn %v4, %v17, %v4
; CHECK-Z14-NEXT: vn %v5, %v16, %v6
; CHECK-Z14-NEXT: vsel %v24, %v3, %v2, %v5
@@ -831,11 +831,11 @@
; CHECK-Z14-NEXT: vfchsb %v4, %v25, %v27
; CHECK-Z14-NEXT: vuphf %v5, %v4
; CHECK-Z14-NEXT: vmrlg %v4, %v4, %v4
-; CHECK-Z14-NEXT: vfchdb %v2, %v24, %v28
-; CHECK-Z14-NEXT: vfchdb %v3, %v26, %v30
-; CHECK-Z14-NEXT: vuphf %v4, %v4
-; CHECK-Z14-NEXT: vl %v0, 176(%r15)
-; CHECK-Z14-NEXT: vl %v1, 160(%r15)
+; CHECK-Z14-DAG: vfchdb %v2, %v24, %v28
+; CHECK-Z14-DAG: vfchdb %v3, %v26, %v30
+; CHECK-Z14-DAG: vuphf %v4, %v4
+; CHECK-Z14-DAG: vl %v0, 176(%r15)
+; CHECK-Z14-DAG: vl %v1, 160(%r15)
; CHECK-Z14-NEXT: vn %v3, %v3, %v4
; CHECK-Z14-NEXT: vn %v2, %v2, %v5
; CHECK-Z14-NEXT: vsel %v24, %v29, %v1, %v2
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-17.ll b/llvm/test/CodeGen/SystemZ/vec-move-17.ll
index 412882d..5a01c90 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-17.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-17.ll
@@ -65,8 +65,8 @@
; CHECK-LABEL: f7:
; CHECK: # %bb.0:
; CHECK-NEXT: vlgvg %r0, %v24, 0
-; CHECK-NEXT: sll %r0, 1
-; CHECK-NEXT: vlgvg %r1, %v24, 1
+; CHECK-DAG: sll %r0, 1
+; CHECK-DAG: vlgvg %r1, %v24, 1
; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 0
; CHECK-NEXT: nilf %r0, 3
; CHECK-NEXT: stc %r0, 0(%r2)
diff --git a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
index 7da1ded..77c93c6 100644
--- a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
@@ -5,12 +5,12 @@
define void @pr32275(<4 x i8> %B15) {
; CHECK-LABEL: pr32275:
; CHECK: # %bb.0: # %BB
-; CHECK-NEXT: vrepif [[REG0:%v[0-9]]], 1
; CHECK: vlgvb %r0, %v24, 3
; CHECK-NEXT: vlgvb %r1, %v24, 1
; CHECK-NEXT: vlvgp [[REG1:%v[0-9]]], %r1, %r0
; CHECK-NEXT: vlgvb %r0, %v24, 0
; CHECK-NEXT: vlgvb [[REG3:%r[0-9]]], %v24, 2
+; CHECK-NEXT: vrepif [[REG0:%v[0-9]]], 1
; CHECK: .LBB0_1:
; CHECK-DAG: vlr [[REG2:%v[0-9]]], [[REG1]]
; CHECK-DAG: vlvgf [[REG2]], %r0, 0