[llvm-exegesis] Improve Register Setup (roll forward of D51856).
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.
Reviewers: courbet, javed.absar
Subscribers: llvm-commits, tschuett, mgorny
Differential Revision: https://reviews.llvm.org/D52297
llvm-svn: 342644
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
index b8533fb..bf5d57e 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
@@ -13,7 +13,7 @@
namespace llvm {
-bool operator==(const llvm::MCOperand &a, const llvm::MCOperand &b) {
+bool operator==(const MCOperand &a, const MCOperand &b) {
if (a.isImm() && b.isImm())
return a.getImm() == b.getImm();
if (a.isReg() && b.isReg())
@@ -21,7 +21,7 @@
return false;
}
-bool operator==(const llvm::MCInst &a, const llvm::MCInst &b) {
+bool operator==(const MCInst &a, const MCInst &b) {
if (a.getOpcode() != b.getOpcode())
return false;
if (a.getNumOperands() != b.getNumOperands())
@@ -41,17 +41,71 @@
namespace {
+using testing::AllOf;
using testing::ElementsAre;
+using testing::ElementsAreArray;
+using testing::Eq;
using testing::Gt;
+using testing::Matcher;
using testing::NotNull;
+using testing::Property;
using testing::SizeIs;
using llvm::APInt;
using llvm::MCInst;
using llvm::MCInstBuilder;
+using llvm::MCOperand;
-constexpr const char kTriple[] = "x86_64-unknown-linux";
+Matcher<MCOperand> IsImm(int64_t Value) {
+ return AllOf(Property(&MCOperand::isImm, Eq(true)),
+ Property(&MCOperand::getImm, Eq(Value)));
+}
+Matcher<MCOperand> IsReg(unsigned Reg) {
+ return AllOf(Property(&MCOperand::isReg, Eq(true)),
+ Property(&MCOperand::getReg, Eq(Reg)));
+}
+
+Matcher<MCInst> OpcodeIs(unsigned Opcode) {
+ return Property(&MCInst::getOpcode, Eq(Opcode));
+}
+
+Matcher<MCInst> IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) {
+ return AllOf(OpcodeIs(Opcode), ElementsAre(IsReg(Reg), IsImm(Value)));
+}
+
+Matcher<MCInst> IsMovValueToStack(unsigned Opcode, int64_t Value,
+ size_t Offset) {
+ return AllOf(OpcodeIs(Opcode),
+ ElementsAre(IsReg(llvm::X86::RSP), IsImm(1), IsReg(0),
+ IsImm(Offset), IsReg(0), IsImm(Value)));
+}
+
+Matcher<MCInst> IsMovValueFromStack(unsigned Opcode, unsigned Reg) {
+ return AllOf(OpcodeIs(Opcode),
+ ElementsAre(IsReg(Reg), IsReg(llvm::X86::RSP), IsImm(1),
+ IsReg(0), IsImm(0), IsReg(0)));
+}
+
+Matcher<MCInst> IsStackAllocate(unsigned Size) {
+ return AllOf(
+ OpcodeIs(llvm::X86::SUB64ri8),
+ ElementsAre(IsReg(llvm::X86::RSP), IsReg(llvm::X86::RSP), IsImm(Size)));
+}
+
+Matcher<MCInst> IsStackDeallocate(unsigned Size) {
+ return AllOf(
+ OpcodeIs(llvm::X86::ADD64ri8),
+ ElementsAre(IsReg(llvm::X86::RSP), IsReg(llvm::X86::RSP), IsImm(Size)));
+}
+
+static const char kTriple[] = "x86_64-unknown-linux";
+static const char kFeaturesEmpty[] = "";
+static const char kFeaturesAvx[] = "+avx";
+static const char kFeaturesAvx512VL[] = "+avx512vl";
+static const char kCpuCore2[] = "core2";
+
+template <const char *CPU, const char *Features>
class X86TargetTest : public ::testing::Test {
protected:
X86TargetTest()
@@ -60,7 +114,9 @@
std::string error;
Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error);
EXPECT_THAT(Target_, NotNull());
+ STI_.reset(Target_->createMCSubtargetInfo(kTriple, kCpuCore2, Features));
}
+
static void SetUpTestCase() {
LLVMInitializeX86TargetInfo();
LLVMInitializeX86Target();
@@ -68,173 +124,208 @@
InitializeX86ExegesisTarget();
}
+ std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
+ return ExegesisTarget_->setRegTo(*STI_, Reg, Value);
+ }
+
const llvm::Target *Target_;
const ExegesisTarget *const ExegesisTarget_;
+ std::unique_ptr<llvm::MCSubtargetInfo> STI_;
};
-TEST_F(X86TargetTest, SetRegToConstantGPR) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", ""));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::EAX);
- EXPECT_THAT(Insts, SizeIs(1));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::MOV32ri);
- EXPECT_EQ(Insts[0].getOperand(0).getReg(), llvm::X86::EAX);
+using Core2TargetTest = X86TargetTest<kCpuCore2, kFeaturesEmpty>;
+using Core2AvxTargetTest = X86TargetTest<kCpuCore2, kFeaturesAvx>;
+using Core2Avx512TargetTest = X86TargetTest<kCpuCore2, kFeaturesAvx512VL>;
+
+TEST_F(Core2TargetTest, SetFlags) {
+ const unsigned Reg = llvm::X86::EFLAGS;
+ EXPECT_THAT(
+ setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
+ ElementsAre(IsStackAllocate(8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
+ OpcodeIs(llvm::X86::POPF64)));
}
-TEST_F(X86TargetTest, SetRegToConstantXMM_SSE2) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", ""));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::XMM1);
- EXPECT_THAT(Insts, SizeIs(7U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOVDQUrm);
- EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2TargetTest, SetRegToGR8Value) {
+ const uint8_t Value = 0xFFU;
+ const unsigned Reg = llvm::X86::AL;
+ EXPECT_THAT(setRegTo(Reg, APInt(8, Value)),
+ ElementsAre(IsMovImmediate(llvm::X86::MOV8ri, Reg, Value)));
}
-TEST_F(X86TargetTest, SetRegToConstantXMM_AVX) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", "+avx"));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::XMM1);
- EXPECT_THAT(Insts, SizeIs(7U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::VMOVDQUrm);
- EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2TargetTest, SetRegToGR16Value) {
+ const uint16_t Value = 0xFFFFU;
+ const unsigned Reg = llvm::X86::BX;
+ EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
+ ElementsAre(IsMovImmediate(llvm::X86::MOV16ri, Reg, Value)));
}
-TEST_F(X86TargetTest, SetRegToConstantXMM_AVX512) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", "+avx512vl"));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::XMM1);
- EXPECT_THAT(Insts, SizeIs(7U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::VMOVDQU32Z128rm);
- EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2TargetTest, SetRegToGR32Value) {
+ const uint32_t Value = 0x7FFFFU;
+ const unsigned Reg = llvm::X86::ECX;
+ EXPECT_THAT(setRegTo(Reg, APInt(32, Value)),
+ ElementsAre(IsMovImmediate(llvm::X86::MOV32ri, Reg, Value)));
}
-TEST_F(X86TargetTest, SetRegToConstantMMX) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", ""));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::MM1);
- EXPECT_THAT(Insts, SizeIs(5U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MMX_MOVQ64rm);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2TargetTest, SetRegToGR64Value) {
+ const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL;
+ const unsigned Reg = llvm::X86::RDX;
+ EXPECT_THAT(setRegTo(Reg, APInt(64, Value)),
+ ElementsAre(IsMovImmediate(llvm::X86::MOV64ri, Reg, Value)));
}
-TEST_F(X86TargetTest, SetRegToConstantYMM_AVX) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", "+avx"));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::YMM1);
- EXPECT_THAT(Insts, SizeIs(11U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[7].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[8].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[9].getOpcode(), llvm::X86::VMOVDQUYrm);
- EXPECT_EQ(Insts[10].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2TargetTest, SetRegToVR64Value) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::MM0, APInt(64, 0x1111222233334444ULL)),
+ ElementsAre(IsStackAllocate(8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
+ IsMovValueFromStack(llvm::X86::MMX_MOVQ64rm, llvm::X86::MM0),
+ IsStackDeallocate(8)));
}
-TEST_F(X86TargetTest, SetRegToConstantYMM_AVX512) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", "+avx512vl"));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::YMM1);
- EXPECT_THAT(Insts, SizeIs(11U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[7].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[8].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[9].getOpcode(), llvm::X86::VMOVDQU32Z256rm);
- EXPECT_EQ(Insts[10].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::XMM0,
+ APInt(128, "11112222333344445555666677778888", 16)),
+ ElementsAre(IsStackAllocate(16),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12),
+ IsMovValueFromStack(llvm::X86::MOVDQUrm, llvm::X86::XMM0),
+ IsStackDeallocate(16)));
}
-TEST_F(X86TargetTest, SetRegToConstantZMM_AVX512) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", "+avx512vl"));
- const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::ZMM1);
- EXPECT_THAT(Insts, SizeIs(19U));
- EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
- EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[7].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[8].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[9].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[10].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[11].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[12].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[13].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[14].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[15].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[16].getOpcode(), llvm::X86::MOV32mi);
- EXPECT_EQ(Insts[17].getOpcode(), llvm::X86::VMOVDQU32Zrm);
- EXPECT_EQ(Insts[18].getOpcode(), llvm::X86::ADD64ri8);
+TEST_F(Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::XMM0,
+ APInt(128, "11112222333344445555666677778888", 16)),
+ ElementsAre(IsStackAllocate(16),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12),
+ IsMovValueFromStack(llvm::X86::VMOVDQUrm, llvm::X86::XMM0),
+ IsStackDeallocate(16)));
}
-TEST_F(X86TargetTest, SetToAPInt) {
- const std::unique_ptr<llvm::MCSubtargetInfo> STI(
- Target_->createMCSubtargetInfo(kTriple, "core2", ""));
- // EXPECT_THAT(ExegesisTarget_->setRegTo(*STI, APInt(8, 0xFFU),
- // llvm::X86::AL),
- // ElementsAre((MCInst)MCInstBuilder(llvm::X86::MOV8ri)
- // .addReg(llvm::X86::AL)
- // .addImm(0xFFU)));
- // EXPECT_THAT(
- // ExegesisTarget_->setRegTo(*STI, APInt(16, 0xFFFFU), llvm::X86::BX),
- // ElementsAre((MCInst)MCInstBuilder(llvm::X86::MOV16ri)
- // .addReg(llvm::X86::BX)
- // .addImm(0xFFFFU)));
- // EXPECT_THAT(
- // ExegesisTarget_->setRegTo(*STI, APInt(32, 0x7FFFFU), llvm::X86::ECX),
- // ElementsAre((MCInst)MCInstBuilder(llvm::X86::MOV32ri)
- // .addReg(llvm::X86::ECX)
- // .addImm(0x7FFFFU)));
- // EXPECT_THAT(ExegesisTarget_->setRegTo(*STI, APInt(64,
- // 0x7FFFFFFFFFFFFFFFULL),
- // llvm::X86::RDX),
- // ElementsAre((MCInst)MCInstBuilder(llvm::X86::MOV64ri)
- // .addReg(llvm::X86::RDX)
- // .addImm(0x7FFFFFFFFFFFFFFFULL)));
+TEST_F(Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::XMM0,
+ APInt(128, "11112222333344445555666677778888", 16)),
+ ElementsAre(
+ IsStackAllocate(16),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12),
+ IsMovValueFromStack(llvm::X86::VMOVDQU32Z128rm, llvm::X86::XMM0),
+ IsStackDeallocate(16)));
+}
- const std::unique_ptr<llvm::MCRegisterInfo> MRI(
- Target_->createMCRegInfo(kTriple));
- const std::unique_ptr<llvm::MCAsmInfo> MAI(
- Target_->createMCAsmInfo(*MRI, kTriple));
- const std::unique_ptr<llvm::MCInstrInfo> MII(Target_->createMCInstrInfo());
- const std::unique_ptr<llvm::MCInstPrinter> MIP(
- Target_->createMCInstPrinter(llvm::Triple(kTriple), 1, *MAI, *MII, *MRI));
+TEST_F(Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) {
+ const char ValueStr[] =
+ "1111111122222222333333334444444455555555666666667777777788888888";
+ EXPECT_THAT(setRegTo(llvm::X86::YMM0, APInt(256, ValueStr, 16)),
+ ElementsAreArray(
+ {IsStackAllocate(32),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 12),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 16),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 20),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 24),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 28),
+ IsMovValueFromStack(llvm::X86::VMOVDQUYrm, llvm::X86::YMM0),
+ IsStackDeallocate(32)}));
+}
- for (const auto M : ExegesisTarget_->setRegTo(
- *STI, APInt(80, "ABCD1234123456785678", 16), llvm::X86::MM0)) {
- MIP->printInst(&M, llvm::errs(), "", *STI);
- llvm::errs() << "\n";
- }
+TEST_F(Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) {
+ const char ValueStr[] =
+ "1111111122222222333333334444444455555555666666667777777788888888";
+ EXPECT_THAT(
+ setRegTo(llvm::X86::YMM0, APInt(256, ValueStr, 16)),
+ ElementsAreArray(
+ {IsStackAllocate(32),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 12),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 16),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 20),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 24),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 28),
+ IsMovValueFromStack(llvm::X86::VMOVDQU32Z256rm, llvm::X86::YMM0),
+ IsStackDeallocate(32)}));
+}
+
+TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) {
+ const char ValueStr[] =
+ "1111111122222222333333334444444455555555666666667777777788888888"
+ "99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000";
+ EXPECT_THAT(
+ setRegTo(llvm::X86::ZMM0, APInt(512, ValueStr, 16)),
+ ElementsAreArray(
+ {IsStackAllocate(64),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0xFFFFFFFFUL, 4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0xEEEEEEEEUL, 8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0xDDDDDDDDUL, 12),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0xCCCCCCCCUL, 16),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0xBBBBBBBBUL, 20),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0xAAAAAAAAUL, 24),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x99999999UL, 28),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 32),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 36),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 40),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 44),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 48),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 52),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 56),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 60),
+ IsMovValueFromStack(llvm::X86::VMOVDQU32Zrm, llvm::X86::ZMM0),
+ IsStackDeallocate(64)}));
+}
+
+TEST_F(Core2TargetTest, SetRegToST0_32Bits) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::ST0, APInt(32, 0x11112222ULL)),
+ ElementsAre(IsStackAllocate(4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
+ OpcodeIs(llvm::X86::LD_F32m), IsStackDeallocate(4)));
+}
+
+TEST_F(Core2TargetTest, SetRegToST1_32Bits) {
+ const MCInst CopySt0ToSt1 =
+ llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(llvm::X86::ST1);
+ EXPECT_THAT(
+ setRegTo(llvm::X86::ST1, APInt(32, 0x11112222ULL)),
+ ElementsAre(IsStackAllocate(4),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
+ OpcodeIs(llvm::X86::LD_F32m), CopySt0ToSt1,
+ IsStackDeallocate(4)));
+}
+
+TEST_F(Core2TargetTest, SetRegToST0_64Bits) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::ST0, APInt(64, 0x1111222233334444ULL)),
+ ElementsAre(IsStackAllocate(8),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
+ OpcodeIs(llvm::X86::LD_F64m), IsStackDeallocate(8)));
+}
+
+TEST_F(Core2TargetTest, SetRegToST0_80Bits) {
+ EXPECT_THAT(
+ setRegTo(llvm::X86::ST0, APInt(80, "11112222333344445555", 16)),
+ ElementsAre(IsStackAllocate(10),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0),
+ IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4),
+ IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8),
+ OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
}
} // namespace