commit ca519dc28b0af4c80b2f8ed8646b81940e8af814
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Jun 04 16:17:34 2015 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Jun 04 16:17:34 2015 +0000
tree d02ad3e42d211d25c4eed9735f7321139351293c
parent a5c092d844939da540d6c91463a1e565cdc487e3

Pass address space to isLegalAddressingMode in DAGCombiner

No test because I don't know of a target that makes use
of address spaces and indexed load / store.

llvm-svn: 239051

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2c2dc85..439ddb2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9061,14 +9061,18 @@
                                     SelectionDAG &DAG,
                                     const TargetLowering &TLI) {
   EVT VT;
+  unsigned AS;
+
   if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(Use)) {
     if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
       return false;
     VT = LD->getMemoryVT();
+    AS = LD->getAddressSpace();
   } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(Use)) {
     if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
       return false;
     VT = ST->getMemoryVT();
+    AS = ST->getAddressSpace();
   } else
     return false;
 
@@ -9092,7 +9096,7 @@
   } else
     return false;
 
-  return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
+  return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()), AS);
 }
 
 /// Try turning a load/store into a pre-indexed load/store when the base