commit ca69a53bae802896a7c3705c52d81f4819ee62ab
author Tom Stellard <thomas.stellard@amd.com> Wed Jul 31 20:43:27 2013 +0000
committer Tom Stellard <thomas.stellard@amd.com> Wed Jul 31 20:43:27 2013 +0000
tree 72b723840529d5c66b0d0290c53d7bc5729dc4f4
parent 0ebf29d41f5e52b7f842468e4230361916abd370

Revert "R600: Non vector only instruction can be scheduled on trans unit"

This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

llvm-svn: 187526

llvm/test/CodeGen/R600/fp_to_sint.ll

diff --git a/llvm/test/CodeGen/R600/fp_to_sint.ll b/llvm/test/CodeGen/R600/fp_to_sint.ll
index c051631..7b430e3 100644
--- a/llvm/test/CodeGen/R600/fp_to_sint.ll
+++ b/llvm/test/CodeGen/R600/fp_to_sint.ll
@@ -2,9 +2,9 @@
 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
 ; R600-CHECK: @fp_to_sint_v4i32
-; R600-CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW]}}
-; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 ; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 ; SI-CHECK: @fp_to_sint_v4i32
 ; SI-CHECK: V_CVT_I32_F32_e32