commit cae2fbd6fc0bc67a881aa6f7fc5e66432d744c63
author Devang Patel <dpatel@apple.com> Tue Apr 26 00:12:46 2011 +0000
committer Devang Patel <dpatel@apple.com> Tue Apr 26 00:12:46 2011 +0000
tree 9d3b0dd9b527ed332ac2bbd5463e2f7b7147a872
parent 420c8de92ec04e30b5c5a69d315675a78ddaacb2

Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.

llvm-svn: 130178

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index b8c117c..10cccda 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -173,10 +173,11 @@
 }
 
 /// EmitDwarfRegOp - Emit dwarf register operation.
-void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
+void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
+                                   unsigned ExtraExprSize) const {
   const TargetRegisterInfo *RI = TM.getRegisterInfo();
   if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
-    AsmPrinter::EmitDwarfRegOp(MLoc);
+    AsmPrinter::EmitDwarfRegOp(MLoc, ExtraExprSize);
   else {
     unsigned Reg = MLoc.getReg();
     if (Reg >= ARM::S0 && Reg <= ARM::S31) {
@@ -191,7 +192,7 @@
       OutStreamer.AddComment("Loc expr size");
       // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
       //   1 + ULEB(Rx) + 1 + 1 + 1
-      EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx));
+      EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx) + ExtraExprSize);
 
       OutStreamer.AddComment("DW_OP_regx for S register");
       EmitInt8(dwarf::DW_OP_regx);
@@ -223,7 +224,8 @@
       // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
       // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
       //   6 + ULEB(D1) + ULEB(D2)
-      EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2));
+      EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) 
+                + MCAsmInfo::getULEB128Size(D2) + ExtraExprSize);
 
       OutStreamer.AddComment("DW_OP_regx for Q register: D1");
       EmitInt8(dwarf::DW_OP_regx);

llvm/lib/Target/ARM/ARMAsmPrinter.h

diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h
index 5f9169e..e949014 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.h
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h
@@ -90,7 +90,8 @@
   MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
 
   /// EmitDwarfRegOp - Emit dwarf register operation.
-  virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
+  virtual void EmitDwarfRegOp(const MachineLocation &MLoc,
+                              unsigned ExtraExprSize = 0) const;
 
   virtual unsigned getISAEncoding() {
     // ARM/Darwin adds ISA to the DWARF info for each function.