Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
diff --git a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
index 1899269..0a9bc3c 100644
--- a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
+++ b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
@@ -13,7 +13,7 @@
;structs at varying alignments. Each test is run for arm, thumb2 and thumb1.
;We check for the strings in the generated object code using llvm-objdump
;because it provides better assurance that we are generating instructions
-;for the correct architecture. Otherwise we could accidently generate an
+;for the correct architecture. Otherwise we could accidentally generate an
;ARM instruction for THUMB1 and wouldn't detect it because the assembly
;code representation is the same, but the object code would be generated
;incorrectly. For each test we check for the label, a load instruction of the
diff --git a/llvm/test/CodeGen/MSP430/misched-msp430.ll b/llvm/test/CodeGen/MSP430/misched-msp430.ll
index 24ca47b..c8541ef 100644
--- a/llvm/test/CodeGen/MSP430/misched-msp430.ll
+++ b/llvm/test/CodeGen/MSP430/misched-msp430.ll
@@ -7,7 +7,7 @@
; Test that the MI Scheduler's initPolicy does not crash when i32 is
; unsupported. The content of the asm check below is unimportant. It
-; only verifies that the code generator ran succesfully.
+; only verifies that the code generator ran successfully.
;
; CHECK-LABEL: @f
; CHECK: mov.w &y, &x
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
index 24e27cbf..f25ab22 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
@@ -10,7 +10,7 @@
; The legalizer legalized ; the <4 x i8>'s into <4 x i32>'s, then a call to
; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt
; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The
-; assertion occured when trying to check the values were bitwise inverses of
+; assertion occurred when trying to check the values were bitwise inverses of
; each-other.
;
; It should at least successfully build.
diff --git a/llvm/test/CodeGen/SystemZ/fp-cmp-04.ll b/llvm/test/CodeGen/SystemZ/fp-cmp-04.ll
index 94f4b7c..781a3be 100644
--- a/llvm/test/CodeGen/SystemZ/fp-cmp-04.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-cmp-04.ll
@@ -1,4 +1,4 @@
-; Test that floating-point compares are ommitted if CC already has the
+; Test that floating-point compares are omitted if CC already has the
; right value.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
diff --git a/llvm/test/CodeGen/SystemZ/frame-08.ll b/llvm/test/CodeGen/SystemZ/frame-08.ll
index da2a614..aa4e3f4 100644
--- a/llvm/test/CodeGen/SystemZ/frame-08.ll
+++ b/llvm/test/CodeGen/SystemZ/frame-08.ll
@@ -208,7 +208,7 @@
ret void
}
-; This is the largest frame size for which the prepatory increment for
+; This is the largest frame size for which the preparatory increment for
; "lmg %r14, %r15, ..." can be done using AGHI.
define void @f5(i32 *%ptr, i64 %x) {
; CHECK-LABEL: f5:
@@ -242,7 +242,7 @@
ret void
}
-; This is the smallest frame size for which the prepatory increment for
+; This is the smallest frame size for which the preparatory increment for
; "lmg %r14, %r15, ..." needs to be done using AGFI.
define void @f6(i32 *%ptr, i64 %x) {
; CHECK-LABEL: f6:
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-44.ll b/llvm/test/CodeGen/SystemZ/int-cmp-44.ll
index 822dcac..f065e64 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-44.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-44.ll
@@ -1,4 +1,4 @@
-; Test that compares are ommitted if CC already has the right value
+; Test that compares are omitted if CC already has the right value
; (z10 version).
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-45.ll b/llvm/test/CodeGen/SystemZ/int-cmp-45.ll
index 753a528..9c9c49c 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-45.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-45.ll
@@ -1,4 +1,4 @@
-; Test that compares are ommitted if CC already has the right value
+; Test that compares are omitted if CC already has the right value
; (z196 version).
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
diff --git a/llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll b/llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
index 3455b68..bbba796 100644
--- a/llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
+++ b/llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
@@ -3,7 +3,7 @@
; During X86 fastisel, the address of indirect call was resolved
; through bitcast, ptrtoint, and inttoptr instructions. This is valid
; only if the related instructions are in that same basic block, otherwise
-; we may reference variables that were not live accross basic blocks
+; we may reference variables that were not live across basic blocks
; resulting in undefined virtual registers.
;
; In this example, this is illustrated by a the spill/reload of the
@@ -25,7 +25,7 @@
; CHECK: movq [[ARG2_SLOT]], %rdi
; Load the second argument
; CHECK: movq [[ARG2_SLOT]], %rsi
-; Load the thrid argument
+; Load the third argument
; CHECK: movq [[ARG2_SLOT]], %rdx
; Load the function pointer.
; CHECK: movq [[LOADED_PTR_SLOT]], [[FCT_PTR:%[a-z]+]]
@@ -64,7 +64,7 @@
; CHECK: movq [[ARG2_SLOT]], %rdi
; Load the second argument
; CHECK: movq [[ARG2_SLOT]], %rsi
-; Load the thrid argument
+; Load the third argument
; CHECK: movq [[ARG2_SLOT]], %rdx
; Load the function pointer.
; CHECK: movq [[LOADED_PTR_SLOT]], [[FCT_PTR:%[a-z]+]]
@@ -103,7 +103,7 @@
; CHECK: movq [[ARG2_SLOT]], %rdi
; Load the second argument
; CHECK: movq [[ARG2_SLOT]], %rsi
-; Load the thrid argument
+; Load the third argument
; CHECK: movq [[ARG2_SLOT]], %rdx
; Load the function pointer.
; CHECK: movq [[LOADED_PTR_SLOT]], [[FCT_PTR:%[a-z]+]]
diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll
index d3e05d6..2681c10 100644
--- a/llvm/test/CodeGen/X86/block-placement.ll
+++ b/llvm/test/CodeGen/X86/block-placement.ll
@@ -701,7 +701,7 @@
define void @unanalyzable_branch_to_best_succ(i1 %cond) {
; Ensure that we can handle unanalyzable branches where the destination block
-; gets selected as the optimal sucessor to merge.
+; gets selected as the optimal successor to merge.
;
; CHECK: unanalyzable_branch_to_best_succ
; CHECK: %entry
diff --git a/llvm/test/CodeGen/X86/load-slice.ll b/llvm/test/CodeGen/X86/load-slice.ll
index 85fd7f0..49eb131 100644
--- a/llvm/test/CodeGen/X86/load-slice.ll
+++ b/llvm/test/CodeGen/X86/load-slice.ll
@@ -6,7 +6,7 @@
%class.Complex = type { float, float }
-; Check that independant slices leads to independant loads then the slices leads to
+; Check that independent slices leads to independent loads then the slices leads to
; different register file.
;
; The layout is:
diff --git a/llvm/test/CodeGen/X86/shl_undef.ll b/llvm/test/CodeGen/X86/shl_undef.ll
index 666c972..705af5b 100644
--- a/llvm/test/CodeGen/X86/shl_undef.ll
+++ b/llvm/test/CodeGen/X86/shl_undef.ll
@@ -4,7 +4,7 @@
; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after
; DAGCombiner optimization pass. These are changed to undef and in turn
; the successor shl(s) become shl undef, 1. This pattern then matches
-; shl x, 1 -> add x, x. add undef, undef doesn't guarentee the low
+; shl x, 1 -> add x, x. add undef, undef doesn't guarantee the low
; order bit is zero and is incorrect.
;
; See rdar://9453156 and rdar://9487392.