[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler
We want to run the Machine Scheduler instead of the List Scheduler after RA.
Checked with a performance run on a Power 9 machine with SPEC 2006 and while
some benchmarks improved and others degraded the geomean was slightly improved
with the Machine Scheduler.
Differential Revision: https://reviews.llvm.org/D45265
llvm-svn: 336295
diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
index 21b6766..bd51ad6 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ilesll(i64 %a, i64 %b) {
@@ -12,7 +12,7 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
@@ -26,7 +26,7 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
@@ -65,11 +65,13 @@
define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r4, 63
-; CHECK: subfc r4, r3, r4
-; CHECK: rldicl r3, r3, 1, 63
-; CHECK: adde r3, r6, r3
-; CHECK: std r3,
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@@ -81,12 +83,14 @@
define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r4, 63
-; CHECK-DAG: rldicl r3, r3, 1, 63
-; CHECK-DAG: subfc r4, r3, r4
-; CHECK: adde r3, r6, r3
-; CHECK: neg r3, r3
-; CHECK: std r3,
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b