AMDGPU/SI: Enable the post-ra scheduler
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Reviewers: arsenm
Subscribers: qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18602
llvm-svn: 268143
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 13abe7f..342afff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -384,6 +384,17 @@
}
void GCNPassConfig::addPreEmitPass() {
+
+ // The hazard recognizer that runs as part of the post-ra scheduler does not
+ // gaurantee to be able handle all hazards correctly. This is because
+ // if there are multiple scheduling regions in a basic block, the regions
+ // are scheduled bottom up, so when we begin to schedule a region we don't
+ // know what instructions were emitted directly before it.
+ //
+ // Here we add a stand-alone hazard recognizer pass which can handle all cases.
+ // hazard recognizer pass.
+ addPass(&PostRAHazardRecognizerID);
+
addPass(createSIInsertWaitsPass(), false);
addPass(createSIShrinkInstructionsPass());
addPass(createSILowerControlFlowPass(), false);