commit cbebba4917f104491013cf1434784bd70bbfc1d6
author Nicolai Haehnle <nhaehnle@gmail.com> Mon Apr 23 13:06:03 2018 +0000
committer Nicolai Haehnle <nhaehnle@gmail.com> Mon Apr 23 13:06:03 2018 +0000
tree ad330baccb3a8f24598fb5b66f6086cddcad54e3
parent 5a995664f07db36071a2584910c22b150a5370a3

AMDGPU: Fix SDWA peephole for V_AND_B32

Summary:
Found by inspection. We care about the operand that *doesn't*
contain the immediate.

I believe this is currently not hit because we fold 0xff / 0xffff
immediates only later.

Change-Id: Ic3cf8538bc7da5eff3200d96eccf9d339e6345a7

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45886

llvm-svn: 330586

llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
index 648f97a..3da63ac 100644
--- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -699,7 +699,7 @@
 
     MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
 
-    if (TRI->isPhysicalRegister(Src1->getReg()) ||
+    if (TRI->isPhysicalRegister(ValSrc->getReg()) ||
         TRI->isPhysicalRegister(Dst->getReg()))
       break;