commit cc3b5590d2a72ab86d58151c4457e7a7fcc89427
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Feb 24 14:08:41 2020 -0500
committer Matt Arsenault <arsenm2@gmail.com> Mon Mar 30 11:26:22 2020 -0400
tree ade6b3545436f4f6f8442e47c6b907d5c5789829
parent 67ebe5de57d1b1ed6d8d04cbd3c3454bbf781f05

GlobalISel: Minor cleanups

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 2aea679..e65d11c 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -35,7 +35,7 @@
                              Register SwiftErrorVReg,
                              std::function<unsigned()> GetCalleeReg) const {
   CallLoweringInfo Info;
-  auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
+  const DataLayout &DL = MIRBuilder.getDataLayout();
 
   // First step is to marshall all the function's parameters into the correct
   // physregs and memory locations. Gather the sequence of argument types that
@@ -62,17 +62,17 @@
   if (!Info.OrigRet.Ty->isVoidTy())
     setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CS);
 
+  MachineFunction &MF = MIRBuilder.getMF();
   Info.KnownCallees =
       CS.getInstruction()->getMetadata(LLVMContext::MD_callees);
   Info.CallConv = CS.getCallingConv();
   Info.SwiftErrorVReg = SwiftErrorVReg;
   Info.IsMustTailCall = CS.isMustTailCall();
   Info.IsTailCall = CS.isTailCall() &&
-                    isInTailCallPosition(CS, MIRBuilder.getMF().getTarget()) &&
-                    (MIRBuilder.getMF()
-                         .getFunction()
-                         .getFnAttribute("disable-tail-calls")
-                         .getValueAsString() != "true");
+                    isInTailCallPosition(CS, MF.getTarget()) &&
+                    (MF.getFunction()
+                       .getFnAttribute("disable-tail-calls")
+                       .getValueAsString() != "true");
   Info.IsVarArg = CS.getFunctionType()->isVarArg();
   return lowerCall(MIRBuilder, Info);
 }
@@ -160,7 +160,7 @@
                               MachineIRBuilder &MIRBuilder) const {
   assert(DstRegs.size() > 1 && "Nothing to unpack");
 
-  const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
+  const DataLayout &DL = MIRBuilder.getDataLayout();
 
   SmallVector<LLT, 8> LLTs;
   SmallVector<uint64_t, 8> Offsets;