[AMDGPU] Rename $dst operand to $vdst for VOP instructions.
Summary: This change renames output operand for VOP instructions from dst to vdst. This is needed to enable decoding named operands for disassembler.
Reviewers: vpykhtin, tstellarAMD, arsenm
Subscribers: arsenm, llvm-commits, nhaustov
Projects: #llvm-amdgpu-spb
Differential Revision: http://reviews.llvm.org/D16920
llvm-svn: 260986
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index a94212a..259638e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -362,8 +362,7 @@
let Inst{63-32} = src2;
}
-class VOP3e <bits<9> op> : Enc64 {
- bits<8> vdst;
+class VOP3a <bits<9> op> : Enc64 {
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
@@ -373,7 +372,6 @@
bits<1> clamp;
bits<2> omod;
- let Inst{7-0} = vdst;
let Inst{8} = src0_modifiers{1};
let Inst{9} = src1_modifiers{1};
let Inst{10} = src2_modifiers{1};
@@ -389,6 +387,20 @@
let Inst{63} = src2_modifiers{0};
}
+class VOP3e <bits<9> op> : VOP3a <op> {
+ bits<8> vdst;
+
+ let Inst{7-0} = vdst;
+}
+
+// Encoding used for VOPC instructions encoded as VOP3
+// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
+class VOP3ce <bits<9> op> : VOP3a <op> {
+ bits<8> sdst;
+
+ let Inst{7-0} = sdst;
+}
+
class VOP3be <bits<9> op> : Enc64 {
bits<8> vdst;
bits<2> src0_modifiers;