fix sse1 only codegen in x86-64 mode, which is something we
apparently try to support.

llvm-svn: 112168
diff --git a/llvm/test/CodeGen/X86/sse1.ll b/llvm/test/CodeGen/X86/sse1.ll
new file mode 100644
index 0000000..2c1acb6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sse1.ll
@@ -0,0 +1,7 @@
+; Tests for SSE1 and below, without SSE2+.
+; RUN: llc < %s -mcpu=pentium3 -O3 | FileCheck %s
+
+define <8 x i16> @test1(<8 x i32> %a) nounwind {
+; CHECK: test1
+  ret <8 x i16> zeroinitializer
+}