commit cca75d24069efb69b10742c1663cbc03bdd0a9a5
author Aditya Nandakumar <aditya_nandakumar@apple.com> Tue Jun 27 22:19:32 2017 +0000
committer Aditya Nandakumar <aditya_nandakumar@apple.com> Tue Jun 27 22:19:32 2017 +0000
tree 279b85928121796dea002e673a977ea8634474f8
parent 650c96e0a73ba27d83da92db55c1b188f393fcd9

[GISel]: Add G_FEXP, G_FEXP2 opcodes

Also add IRTranslator support.
https://reviews.llvm.org/D34710

llvm-svn: 306475

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index ecfa660..fcaa1fb 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -720,6 +720,16 @@
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
         .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
     return true;
+  case Intrinsic::exp:
+    MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
+  case Intrinsic::exp2:
+    MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
   case Intrinsic::fma:
     MIRBuilder.buildInstr(TargetOpcode::G_FMA)
         .addDef(getOrCreateVReg(CI))