ARM: update subtarget information for Windows on ARM
Update the subtarget information for Windows on ARM. This enables using the MC
layer to target Windows on ARM.
llvm-svn: 205459
diff --git a/llvm/test/CodeGen/ARM/Windows/aapcs.ll b/llvm/test/CodeGen/ARM/Windows/aapcs.ll
new file mode 100644
index 0000000..3f9a09f
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/aapcs.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s
+
+; AAPCS mandates an 8-byte stack alignment. The alloca is implicitly aligned,
+; and no bic is required.
+
+declare void @callee(i8 *%i)
+
+define void @caller() {
+ %i = alloca i8, align 8
+ call void @callee(i8* %i)
+ ret void
+}
+
+; CHECK: sub sp, #8
+; CHECK-NOT: bic
+
diff --git a/llvm/test/CodeGen/ARM/Windows/hard-float.ll b/llvm/test/CodeGen/ARM/Windows/hard-float.ll
new file mode 100644
index 0000000..f7b7ec2
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/hard-float.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s
+
+define float @function(float %f, float %g) nounwind {
+entry:
+ %h = fadd float %f, %g
+ ret float %h
+}
+
+; CHECK: vadd.f32 s0, s0, s1
+
diff --git a/llvm/test/CodeGen/ARM/Windows/mangling.ll b/llvm/test/CodeGen/ARM/Windows/mangling.ll
new file mode 100644
index 0000000..ce1fe2e
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/mangling.ll
@@ -0,0 +1,9 @@
+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -o - %s | FileCheck %s
+
+define void @function() nounwind {
+entry:
+ ret void
+}
+
+; CHECK-LABEL: function
+
diff --git a/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll b/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll
new file mode 100644
index 0000000..4c6676f
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s
+
+define i32 @divide(i32 %i, i32 %j) nounwind {
+entry:
+ %quotient = sdiv i32 %i, %j
+ ret i32 %quotient
+}
+
+; CHECK-NOT: __aeabi_idiv
+
diff --git a/llvm/test/CodeGen/ARM/Windows/no-arm-mode.ll b/llvm/test/CodeGen/ARM/Windows/no-arm-mode.ll
new file mode 100644
index 0000000..6db031f
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/no-arm-mode.ll
@@ -0,0 +1,5 @@
+; RUN: not llc -mtriple=armv7-windows-itanium -mcpu=cortex-a9 -o /dev/null %s 2>&1 \
+; RUN: | FileCheck %s
+
+; CHECK: does not support ARM mode execution
+
diff --git a/llvm/test/CodeGen/ARM/Windows/no-ehabi.ll b/llvm/test/CodeGen/ARM/Windows/no-ehabi.ll
new file mode 100644
index 0000000..4119b6d
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/no-ehabi.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -o - %s | FileCheck %s
+
+declare void @callee(i32 %i)
+
+define i32 @caller(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o,
+ i32 %p) {
+entry:
+ %q = add nsw i32 %j, %i
+ %r = add nsw i32 %q, %k
+ %s = add nsw i32 %r, %l
+ call void @callee(i32 %s)
+ %t = add nsw i32 %n, %m
+ %u = add nsw i32 %t, %o
+ %v = add nsw i32 %u, %p
+ call void @callee(i32 %v)
+ %w = add nsw i32 %v, %s
+ ret i32 %w
+}
+
+; CHECK-NOT: .save {{{.*}}}
+