ARM parsing aliases for VLD1 single register all lanes.

llvm-svn: 145464
diff --git a/llvm/utils/TableGen/EDEmitter.cpp b/llvm/utils/TableGen/EDEmitter.cpp
index 1953dad..0a7e251 100644
--- a/llvm/utils/TableGen/EDEmitter.cpp
+++ b/llvm/utils/TableGen/EDEmitter.cpp
@@ -576,6 +576,7 @@
   REG("VecListThreeD");
   REG("VecListFourD");
   REG("VecListTwoQ");
+  REG("VecListOneDAllLanes");
 
   IMM("i32imm");
   IMM("i32imm_hilo16");