commit cd9da22f68eeef24eed299191c26576e020167a6
author Owen Anderson <resistor@mac.com> Mon Nov 01 18:33:37 2010 +0000
committer Owen Anderson <resistor@mac.com> Mon Nov 01 18:33:37 2010 +0000
tree 25ee15841d6ed48a4f313d191e6d5a947bf8a6a7
parent 44be217af1e633087861153096895a3efc6cdef7

Use ARM-style comment syntax.

llvm-svn: 117941

llvm/test/MC/ARM/neon-reverse-encoding.s

diff --git a/llvm/test/MC/ARM/neon-reverse-encoding.s b/llvm/test/MC/ARM/neon-reverse-encoding.s
index 1b538b8..54e750b 100644
--- a/llvm/test/MC/ARM/neon-reverse-encoding.s
+++ b/llvm/test/MC/ARM/neon-reverse-encoding.s
@@ -1,26 +1,26 @@
-// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
 
-// CHECK: vrev64.8	d16, d16        @ encoding: [0x20,0x00,0xf0,0xf3]
+@ CHECK: vrev64.8	d16, d16        @ encoding: [0x20,0x00,0xf0,0xf3]
 	vrev64.8	d16, d16
-// CHECK: vrev64.16	d16, d16        @ encoding: [0x20,0x00,0xf4,0xf3]
+@ CHECK: vrev64.16	d16, d16        @ encoding: [0x20,0x00,0xf4,0xf3]
 	vrev64.16	d16, d16
-// CHECK: vrev64.32	d16, d16        @ encoding: [0x20,0x00,0xf8,0xf3]
+@ CHECK: vrev64.32	d16, d16        @ encoding: [0x20,0x00,0xf8,0xf3]
 	vrev64.32	d16, d16
-// CHECK: vrev64.8	q8, q8          @ encoding: [0x60,0x00,0xf0,0xf3]
+@ CHECK: vrev64.8	q8, q8          @ encoding: [0x60,0x00,0xf0,0xf3]
 	vrev64.8	q8, q8
-// CHECK: vrev64.16	q8, q8          @ encoding: [0x60,0x00,0xf4,0xf3]
+@ CHECK: vrev64.16	q8, q8          @ encoding: [0x60,0x00,0xf4,0xf3]
 	vrev64.16	q8, q8
-// CHECK: vrev64.32	q8, q8          @ encoding: [0x60,0x00,0xf8,0xf3]
+@ CHECK: vrev64.32	q8, q8          @ encoding: [0x60,0x00,0xf8,0xf3]
 	vrev64.32	q8, q8
-// CHECK: vrev32.8	d16, d16        @ encoding: [0xa0,0x00,0xf0,0xf3]
+@ CHECK: vrev32.8	d16, d16        @ encoding: [0xa0,0x00,0xf0,0xf3]
 	vrev32.8	d16, d16
-// CHECK: vrev32.16	d16, d16        @ encoding: [0xa0,0x00,0xf4,0xf3]
+@ CHECK: vrev32.16	d16, d16        @ encoding: [0xa0,0x00,0xf4,0xf3]
 	vrev32.16	d16, d16
-// CHECK: vrev32.8	q8, q8          @ encoding: [0xe0,0x00,0xf0,0xf3]
+@ CHECK: vrev32.8	q8, q8          @ encoding: [0xe0,0x00,0xf0,0xf3]
 	vrev32.8	q8, q8
-// CHECK: vrev32.16	q8, q8          @ encoding: [0xe0,0x00,0xf4,0xf3]
+@ CHECK: vrev32.16	q8, q8          @ encoding: [0xe0,0x00,0xf4,0xf3]
 	vrev32.16	q8, q8
-// CHECK: vrev16.8	d16, d16        @ encoding: [0x20,0x01,0xf0,0xf3]
+@ CHECK: vrev16.8	d16, d16        @ encoding: [0x20,0x01,0xf0,0xf3]
 	vrev16.8	d16, d16
-// CHECK: vrev16.8	q8, q8          @ encoding: [0x60,0x01,0xf0,0xf3]
+@ CHECK: vrev16.8	q8, q8          @ encoding: [0x60,0x01,0xf0,0xf3]
 	vrev16.8	q8, q8