diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 300a100..77907ac 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -26,7 +26,9 @@
     Record *R = *I;
     if (R->getName() == "PHI" ||
         R->getName() == "INLINEASM" ||
-        R->getName() == "LABEL") continue;
+        R->getName() == "LABEL" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -97,7 +99,9 @@
     
     if (R->getName() == "PHI" ||
         R->getName() == "INLINEASM" ||
-        R->getName() == "LABEL") {
+        R->getName() == "LABEL" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG") {
       o << "    0U";
       continue;
     }
@@ -127,7 +131,9 @@
     
     if (InstName == "PHI" ||
         InstName == "INLINEASM" ||
-        InstName == "LABEL") continue;
+        InstName == "LABEL"||
+        InstName == "EXTRACT_SUBREG" ||
+        InstName == "INSERT_SUBREG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 7952ca7..21136c4 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -275,14 +275,28 @@
   if (I == Instructions.end()) throw "Could not find 'LABEL' instruction!";
   const CodeGenInstruction *LABEL = &I->second;
   
+  I = getInstructions().find("EXTRACT_SUBREG");
+  if (I == Instructions.end()) 
+    throw "Could not find 'EXTRACT_SUBREG' instruction!";
+  const CodeGenInstruction *EXTRACT_SUBREG = &I->second;
+  
+  I = getInstructions().find("INSERT_SUBREG");
+  if (I == Instructions.end()) 
+    throw "Could not find 'INSERT_SUBREG' instruction!";
+  const CodeGenInstruction *INSERT_SUBREG = &I->second;
+  
   // Print out the rest of the instructions now.
   NumberedInstructions.push_back(PHI);
   NumberedInstructions.push_back(INLINEASM);
   NumberedInstructions.push_back(LABEL);
+  NumberedInstructions.push_back(EXTRACT_SUBREG);
+  NumberedInstructions.push_back(INSERT_SUBREG);
   for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
     if (&II->second != PHI &&
         &II->second != INLINEASM &&
-        &II->second != LABEL)
+        &II->second != LABEL &&
+        &II->second != EXTRACT_SUBREG &&
+        &II->second != INSERT_SUBREG)
       NumberedInstructions.push_back(&II->second);
 }
 
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 36677bb..b5b2ba1 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -3729,6 +3729,33 @@
      << "                               MVT::Other, Tmp, Chain);\n"
      << "}\n\n";
 
+  OS << "SDNode *Select_EXTRACT_SUBREG(const SDOperand &N) {\n"
+     << "  SDOperand N0 = N.getOperand(0);\n"
+     << "  SDOperand N1 = N.getOperand(1);\n"
+     << "  unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
+     << "  SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+     << "  AddToISelQueue(N0);\n"
+     << "  return CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,\n"
+     << "                             N.getValueType(), N0, Tmp);\n"
+     << "}\n\n";
+
+  OS << "SDNode *Select_INSERT_SUBREG(const SDOperand &N) {\n"
+     << "  SDOperand N0 = N.getOperand(0);\n"
+     << "  SDOperand N1 = N.getOperand(1);\n"
+     << "  SDOperand N2 = N.getOperand(2);\n"
+     << "  unsigned C = cast<ConstantSDNode>(N2)->getValue();\n"
+     << "  SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+     << "  AddToISelQueue(N1);\n"
+     << "  if (N0.getOpcode() == ISD::UNDEF) {\n"
+     << "    return CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,\n"
+     << "                                    N.getValueType(), N1, Tmp);\n"
+     << "  } else {\n"
+     << "    AddToISelQueue(N0);\n"
+     << "    return CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,\n"
+     << "                                    N.getValueType(), N0, N1, Tmp);\n"
+     << "  }\n"
+     << "}\n\n";
+
   OS << "// The main instruction selector code.\n"
      << "SDNode *SelectCode(SDOperand N) {\n"
      << "  if (N.getOpcode() >= ISD::BUILTIN_OP_END &&\n"
@@ -3766,7 +3793,9 @@
      << "    return NULL;\n"
      << "  }\n"
      << "  case ISD::INLINEASM: return Select_INLINEASM(N);\n"
-     << "  case ISD::LABEL: return Select_LABEL(N);\n";
+     << "  case ISD::LABEL: return Select_LABEL(N);\n"
+     << "  case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n"
+     << "  case ISD::INSERT_SUBREG:  return Select_INSERT_SUBREG(N);\n";
 
     
   // Loop over all of the case statements, emiting a call to each method we
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index da2308e..9a5dd2b 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -325,7 +325,9 @@
     // This isn't an error if this is a builtin instruction.
     if (R->getName() != "PHI" &&
         R->getName() != "INLINEASM" &&
-        R->getName() != "LABEL")
+        R->getName() != "LABEL" &&
+        R->getName() != "EXTRACT_SUBREG" &&
+        R->getName() != "INSERT_SUBREG")
       throw R->getName() + " doesn't have a field named '" + 
             Val->getValue() + "'!";
     return;