commit cdf58092e42c01d0fb0f071ea54689cbcc93fc47
author Simon Pilgrim <llvm-dev@redking.me.uk> Fri Jan 25 11:34:58 2019 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Fri Jan 25 11:34:58 2019 +0000
tree 0ac4df1a796840337624d166af2c5fec58475247
parent e5116e9b4aa3a8a3c0df292d456f321813d7ff64

Fix gcc -Wparentheses warning. NFCI.

llvm-svn: 352191

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index c4cd1a3..2c23170 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -177,8 +177,8 @@
     // would require an agreement on the type of registers with the
     // target. Currently createVRegs just uses scalar types, and expects the
     // target code to replace this type (which we won't know about here)
-    assert(RegTy.isScalar() ||
-           (RegTy.getNumElements() == ValMapping.NumBreakDowns) &&
+    assert((RegTy.isScalar() ||
+            RegTy.getNumElements() == ValMapping.NumBreakDowns) &&
            "only basic vector breakdowns currently supported");
 
     if (MO.isDef()) {