[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available.
The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers!
llvm-svn: 214634
diff --git a/llvm/test/CodeGen/AArch64/paired-load.ll b/llvm/test/CodeGen/AArch64/paired-load.ll
new file mode 100644
index 0000000..35c9050
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/paired-load.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios5.0.0"
+
+; Ensure we're generating ldp instructions instead of ldr Q.
+; CHECK: ldp
+; CHECK: stp
+define void @f(i64* %p, i64* %q) {
+ %addr2 = getelementptr i64* %q, i32 1
+ %addr = getelementptr i64* %p, i32 1
+ %x = load i64* %p
+ %y = load i64* %addr
+ store i64 %x, i64* %q
+ store i64 %y, i64* %addr2
+ ret void
+}