[SDAG] Revert r296476 (and r296486, r296668, r296690).
This patch causes compile times for some patterns to explode. I have
a (large, unreduced) test case that slows down by more than 20x and
several test cases slow down by 2x. I'm sending some of the test cases
directly to Nirav and following up with more details in the review log,
but this should unblock anyone else hitting this.
llvm-svn: 296862
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
index 004f6d9..7d32992 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
@@ -63,39 +63,39 @@
; NEW-DAG: sd $5, 16([[R2]])
; O32 has run out of argument registers and starts using the stack
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 16($sp)
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp)
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)
; O32-DAG: sw [[R3]], 24([[R2]])
; O32-DAG: sw [[R4]], 28([[R2]])
; NEW-DAG: sd $6, 24([[R2]])
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
; O32-DAG: sw [[R3]], 32([[R2]])
; O32-DAG: sw [[R4]], 36([[R2]])
; NEW-DAG: sd $7, 32([[R2]])
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
; O32-DAG: sw [[R3]], 40([[R2]])
; O32-DAG: sw [[R4]], 44([[R2]])
; NEW-DAG: sd $8, 40([[R2]])
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
; O32-DAG: sw [[R3]], 48([[R2]])
; O32-DAG: sw [[R4]], 52([[R2]])
; NEW-DAG: sd $9, 48([[R2]])
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp)
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp)
; O32-DAG: sw [[R3]], 56([[R2]])
; O32-DAG: sw [[R4]], 60([[R2]])
; NEW-DAG: sd $10, 56([[R2]])
; N32/N64 have run out of registers and starts using the stack too
-; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp)
-; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)
+; O32-DAG: lw [[R3:\$[0-9]+]], 64($sp)
+; O32-DAG: lw [[R4:\$[0-9]+]], 68($sp)
; O32-DAG: sw [[R3]], 64([[R2]])
; O32-DAG: sw [[R4]], 68([[R2]])
; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
index d662128..785188b 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
@@ -315,11 +315,12 @@
; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
; order.
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]])
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 8([[GV]])
-; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4
-; O32-DAG: sw [[VA3]], 0([[SP]])
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]])
+; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
+; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
+; O32-DAG: sw [[VA2]], 0([[SP]])
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 12([[GV]])
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
@@ -348,9 +349,10 @@
; Load the second argument from the variable portion and copy it to the global.
; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG2]], 16([[GV]])
-; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4
-; O32-DAG: sw [[VA3]], 0([[SP]])
-; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]])
+; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
+; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
+; O32-DAG: sw [[VA2]], 0([[SP]])
+; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG2]], 20([[GV]])
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])
@@ -676,11 +678,12 @@
; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
; order.
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]])
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 8([[GV]])
-; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4
-; O32-DAG: sw [[VA3]], 0([[SP]])
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]])
+; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
+; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
+; O32-DAG: sw [[VA2]], 0([[SP]])
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 12([[GV]])
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
@@ -709,9 +712,10 @@
; Load the second argument from the variable portion and copy it to the global.
; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG2]], 16([[GV]])
-; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4
+; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
+; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]])
-; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]])
+; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG2]], 20([[GV]])
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])
@@ -1036,9 +1040,10 @@
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 8([[GV]])
-; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4
-; O32-DAG: sw [[VA3]], 0([[SP]])
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]])
+; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
+; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
+; O32-DAG: sw [[VA2]], 0([[SP]])
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 12([[GV]])
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
@@ -1067,9 +1072,10 @@
; Load the second argument from the variable portion and copy it to the global.
; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG2]], 16([[GV]])
-; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4
-; O32-DAG: sw [[VA3]], 0([[SP]])
-; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]])
+; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
+; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
+; O32-DAG: sw [[VA2]], 0([[SP]])
+; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG2]], 20([[GV]])
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])
diff --git a/llvm/test/CodeGen/Mips/fastcc.ll b/llvm/test/CodeGen/Mips/fastcc.ll
index fb1bc4d..13abc20 100644
--- a/llvm/test/CodeGen/Mips/fastcc.ll
+++ b/llvm/test/CodeGen/Mips/fastcc.ll
@@ -132,19 +132,20 @@
define internal fastcc void @callee0(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) nounwind noinline {
entry:
; CHECK: callee0
-; CHECK-DAG: sw $4
-; CHECK-DAG: sw $5
-; CHECK-DAG: sw $7
-; CHECK-DAG: sw $8
-; CHECK-DAG: sw $9
-; CHECK-DAG: sw $10
-; CHECK-DAG: sw $11
-; CHECK-DAG: sw $12
-; CHECK-DAG: sw $13
-; CHECK-DAG: sw $14
-; CHECK-DAG: sw $15
-; CHECK-DAG: sw $24
-; CHECK-DAG: sw $3
+; CHECK: sw $4
+; CHECK: sw $5
+; CHECK: sw $6
+; CHECK: sw $7
+; CHECK: sw $8
+; CHECK: sw $9
+; CHECK: sw $10
+; CHECK: sw $11
+; CHECK: sw $12
+; CHECK: sw $13
+; CHECK: sw $14
+; CHECK: sw $15
+; CHECK: sw $24
+; CHECK: sw $3
; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
; CHECK-NACL-NOT: sw $14
@@ -222,27 +223,27 @@
define internal fastcc void @callee1(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15, float %a16, float %a17, float %a18, float %a19, float %a20) nounwind noinline {
entry:
-; CHECK-LABEL: callee1:
-; CHECK-DAG: swc1 $f0
-; CHECK-DAG: swc1 $f1
-; CHECK-DAG: swc1 $f2
-; CHECK-DAG: swc1 $f3
-; CHECK-DAG: swc1 $f4
-; CHECK-DAG: swc1 $f5
-; CHECK-DAG: swc1 $f6
-; CHECK-DAG: swc1 $f7
-; CHECK-DAG: swc1 $f8
-; CHECK-DAG: swc1 $f9
-; CHECK-DAG: swc1 $f10
-; CHECK-DAG: swc1 $f11
-; CHECK-DAG: swc1 $f12
-; CHECK-DAG: swc1 $f13
-; CHECK-DAG: swc1 $f14
-; CHECK-DAG: swc1 $f15
-; CHECK-DAG: swc1 $f16
-; CHECK-DAG: swc1 $f17
-; CHECK-DAG: swc1 $f18
-; CHECK-DAG: swc1 $f19
+; CHECK: callee1
+; CHECK: swc1 $f0
+; CHECK: swc1 $f1
+; CHECK: swc1 $f2
+; CHECK: swc1 $f3
+; CHECK: swc1 $f4
+; CHECK: swc1 $f5
+; CHECK: swc1 $f6
+; CHECK: swc1 $f7
+; CHECK: swc1 $f8
+; CHECK: swc1 $f9
+; CHECK: swc1 $f10
+; CHECK: swc1 $f11
+; CHECK: swc1 $f12
+; CHECK: swc1 $f13
+; CHECK: swc1 $f14
+; CHECK: swc1 $f15
+; CHECK: swc1 $f16
+; CHECK: swc1 $f17
+; CHECK: swc1 $f18
+; CHECK: swc1 $f19
store float %a0, float* @gf0, align 4
store float %a1, float* @gf1, align 4
@@ -315,6 +316,8 @@
; NOODDSPREG-LABEL: callee2:
+; NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]]
+
; Check that first 10 arguments are received in even float registers
; f0, f2, ... , f18. Check that 11th argument is received on stack.
@@ -330,7 +333,7 @@
; NOODDSPREG-DAG: swc1 $f16, 32($[[R0]])
; NOODDSPREG-DAG: swc1 $f18, 36($[[R0]])
-; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], 0($sp)
+; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)
; NOODDSPREG-DAG: swc1 $[[F0]], 40($[[R0]])
store float %a0, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 0), align 4
@@ -394,6 +397,7 @@
; FP64-NOODDSPREG-LABEL: callee3:
+; FP64-NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]]
; Check that first 10 arguments are received in even float registers
; f0, f2, ... , f18. Check that 11th argument is received on stack.
@@ -410,7 +414,7 @@
; FP64-NOODDSPREG-DAG: sdc1 $f16, 64($[[R0]])
; FP64-NOODDSPREG-DAG: sdc1 $f18, 72($[[R0]])
-; FP64-NOODDSPREG-DAG: ldc1 $[[F0:f[0-9]*[02468]]], 0($sp)
+; FP64-NOODDSPREG-DAG: ldc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)
; FP64-NOODDSPREG-DAG: sdc1 $[[F0]], 80($[[R0]])
store double %a0, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 0), align 8
diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll
index 6def55c..3bd924a 100644
--- a/llvm/test/CodeGen/Mips/load-store-left-right.ll
+++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll
@@ -250,18 +250,12 @@
; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
-; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS32-DAG: sb $[[R1]], 2($[[PTR]])
-; MIPS32-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]])
-; MIPS32-DAG: sb $[[R2]], 3($[[PTR]])
-
-; MIPS32R6: lhu $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS32R6: sh $[[R1]], 2($[[PTR]])
-
-; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64-DAG: sb $[[R1]], 2($[[PTR]])
-; MIPS64-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]])
-; MIPS64-DAG: sb $[[R2]], 3($[[PTR]])
+; FIXME: We should be able to do better than this on MIPS32r6/MIPS64r6 since
+; we have unaligned halfword load/store available
+; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
+; ALL-DAG: sb $[[R1]], 2($[[PTR]])
+; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
+; ALL-DAG: sb $[[R1]], 3($[[PTR]])
%0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1
store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1
@@ -274,54 +268,37 @@
; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s1)(
; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s1)(
-; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
-; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]])
-; MIPS32-EL-DAG: swl $[[R1]], 7($[[PTR]])
-; MIPS32-EL-DAG: swr $[[R1]], 4($[[PTR]])
-; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]])
-; MIPS32-EB-DAG: swl $[[R1]], 4($[[PTR]])
-; MIPS32-EB-DAG: swr $[[R1]], 7($[[PTR]])
-
-; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
-; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]])
+; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS32-DAG: sb $[[R1]], 4($[[PTR]])
+; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
+; MIPS32-DAG: sb $[[R1]], 5($[[PTR]])
+; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
+; MIPS32-DAG: sb $[[R1]], 6($[[PTR]])
+; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
+; MIPS32-DAG: sb $[[R1]], 7($[[PTR]])
; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s1)(
-; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS32R6-DAG: sw $[[R1]], 4($[[PTR]])
+; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS32R6-DAG: sh $[[R1]], 4($[[PTR]])
+; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])
+; MIPS32R6-DAG: sh $[[R1]], 6($[[PTR]])
; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
-
-; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
-; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])
-; MIPS64-EL-DAG: swl $[[R1]], 7($[[PTR]])
-; MIPS64-EL-DAG: swr $[[R1]], 4($[[PTR]])
-
-; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])
-; MIPS64-EB-DAG: swl $[[R1]], 4($[[PTR]])
-; MIPS64-EB-DAG: swr $[[R1]], 7($[[PTR]])
-
-
-; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
-; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]])
+; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64-DAG: sb $[[R1]], 4($[[PTR]])
+; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
+; MIPS64-DAG: sb $[[R1]], 5($[[PTR]])
+; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
+; MIPS64-DAG: sb $[[R1]], 6($[[PTR]])
+; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
+; MIPS64-DAG: sb $[[R1]], 7($[[PTR]])
; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
-; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64R6-DAG: sw $[[R1]], 4($[[PTR]])
+; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64R6-DAG: sh $[[R1]], 4($[[PTR]])
+; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])
+; MIPS64R6-DAG: sh $[[R1]], 6($[[PTR]])
%0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1
store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1
@@ -359,21 +336,30 @@
; MIPS32R6-DAG: sw $[[R1]], 12($[[PTR]])
; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
-
-; MIPS64-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]])
-; MIPS64-EL-DAG: ldr $[[R1]], 0($[[PTR]])
-; MIPS64-EL-DAG: sdl $[[R1]], 15($[[PTR]])
-; MIPS64-EL-DAG: sdr $[[R1]], 8($[[PTR]])
+; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
+; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])
+; MIPS64-EL-DAG: swl $[[R1]], 11($[[PTR]])
+; MIPS64-EL-DAG: swr $[[R1]], 8($[[PTR]])
+; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]])
+; MIPS64-EL-DAG: lwr $[[R1]], 4($[[PTR]])
+; MIPS64-EL-DAG: swl $[[R1]], 15($[[PTR]])
+; MIPS64-EL-DAG: swr $[[R1]], 12($[[PTR]])
; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
-; MIPS64-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64-EB-DAG: ldr $[[R1]], 7($[[PTR]])
-; MIPS64-EB-DAG: sdl $[[R1]], 8($[[PTR]])
-; MIPS64-EB-DAG: sdr $[[R1]], 15($[[PTR]])
+; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])
+; MIPS64-EB-DAG: swl $[[R1]], 8($[[PTR]])
+; MIPS64-EB-DAG: swr $[[R1]], 11($[[PTR]])
+; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]])
+; MIPS64-EB-DAG: lwr $[[R1]], 7($[[PTR]])
+; MIPS64-EB-DAG: swl $[[R1]], 12($[[PTR]])
+; MIPS64-EB-DAG: swr $[[R1]], 15($[[PTR]])
; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
-; MIPS64R6-DAG: ld $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64R6-DAG: sd $[[R1]], 8($[[PTR]])
+; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64R6-DAG: sw $[[R1]], 8($[[PTR]])
+; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]])
+; MIPS64R6-DAG: sw $[[R1]], 12($[[PTR]])
%0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1
store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1
@@ -430,17 +416,17 @@
; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])
-; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
+; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
+; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])
+; MIPS64-EB-DAG: dsll $[[R1]], $[[R1]], 32
; MIPS64-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]])
; MIPS64-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]])
; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8
; MIPS64-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]]
-; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])
; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16
-; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
-; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])
-; MIPS64-EB-DAG: dsll $[[R5:[0-9]+]], $[[R1]], 32
-; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R5]], $[[T1]]
+; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R1]], $[[T1]]
+; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])
; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8
; MIPS64-EB-DAG: or $4, $[[T3]], $[[T4]]
diff --git a/llvm/test/CodeGen/Mips/micromips-li.ll b/llvm/test/CodeGen/Mips/micromips-li.ll
index 997f4e9..ac315f9 100644
--- a/llvm/test/CodeGen/Mips/micromips-li.ll
+++ b/llvm/test/CodeGen/Mips/micromips-li.ll
@@ -13,6 +13,6 @@
ret i32 0
}
-; CHECK: addiu ${{[0-9]+}}, $zero, 2148
; CHECK: li16 ${{[2-7]|16|17}}, 1
+; CHECK: addiu ${{[0-9]+}}, $zero, 2148
; CHECK: ori ${{[0-9]+}}, $zero, 33332
diff --git a/llvm/test/CodeGen/Mips/mips64-f128-call.ll b/llvm/test/CodeGen/Mips/mips64-f128-call.ll
index 19fa8fc..c59f25e 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128-call.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128-call.ll
@@ -4,8 +4,8 @@
@gld1 = external global fp128
; CHECK: foo0
-; CHECK-DAG: sdc1 $f12, %lo(gld0)(${{[0-9]+}})
-; CHECK-DAG: sdc1 $f13, 8(${{[0-9]+}})
+; CHECK: sdc1 $f12, %lo(gld0)(${{[0-9]+}})
+; CHECK: sdc1 $f13, 8(${{[0-9]+}})
define void @foo0(fp128 %a0) {
entry:
@@ -14,8 +14,8 @@
}
; CHECK: foo1
-; CHECK-DAG: ldc1 $f12, %lo(gld0)(${{[0-9]+}})
-; CHECK-DAG: ldc1 $f13, 8(${{[0-9]+}})
+; CHECK: ldc1 $f12, %lo(gld0)(${{[0-9]+}})
+; CHECK: ldc1 $f13, 8(${{[0-9]+}})
define void @foo1() {
entry:
@@ -26,11 +26,11 @@
declare void @foo2(fp128)
-
; CHECK: foo3:
-
-; CHECK: daddiu $[[R2:[0-9]+]], $[[R1:[0-9]+]], %lo(gld0)
+; CHECK: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(gld0)
+; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 16
; CHECK: sdc1 $f0, %lo(gld0)($[[R1]])
+; CHECK: daddiu $[[R2:[0-9]]], $[[R1]], %lo(gld0)
; CHECK: sdc1 $f2, 8($[[R2]])
; CHECK: daddiu $[[R3:[0-9]+]], ${{[0-9]+}}, %hi(gld1)
; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 16
@@ -39,6 +39,7 @@
; CHECK: ldc1 $f2, 8($[[R5]])
+
define fp128 @foo3() {
entry:
%call = tail call fp128 @foo4()
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index 237b4c5..304ab8b 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -577,10 +577,10 @@
; ALL-LABEL: store_LD_LD:
; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)
+; ALL: ld $[[R1:[0-9]+]], 0($[[R0]])
; ALL: ld $[[R2:[0-9]+]], 8($[[R0]])
; ALL: ld $[[R3:[0-9]+]], %got_disp(gld0)
; ALL: sd $[[R2]], 8($[[R3]])
-; ALL: ld $[[R1:[0-9]+]], 0($[[R0]])
; ALL: sd $[[R1]], 0($[[R3]])
define void @store_LD_LD() {
diff --git a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index 0260afa..9663138 100644
--- a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -130,12 +130,12 @@
; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25
; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]])
-; MM-MNO-PIC-DAG: lw16 $[[R4:[0-9]+]], 0($[[R3]])
-; MM-MNO-PIC-DAG: lw16 $[[R5:[0-9]+]], 4($[[R3]])
-; MM-MNO-LE-PIC-DAG: mtc1 $[[R4]], $f0
-; MM-MNO-LE-PIC-DAG: mthc1 $[[R5]], $f0
-; MM-MNO-BE-PIC-DAG: mtc1 $[[R5]], $f0
-; MM-MNO-BE-PIC-DAG: mthc1 $[[R4]], $f0
+; MM-MNO-PIC: lw16 $[[R4:[0-9]+]], 0($[[R3]])
+; MM-MNO-PIC: lw16 $[[R5:[0-9]+]], 4($[[R3]])
+; MM-MNO-LE-PIC: mtc1 $[[R4]], $f0
+; MM-MNO-LE-PIC: mthc1 $[[R5]], $f0
+; MM-MNO-BE-PIC: mtc1 $[[R5]], $f0
+; MM-MNO-BE-PIC: mthc1 $[[R4]], $f0
; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0)
; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]])
@@ -214,13 +214,13 @@
; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp)
; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25
-; MM-MNO-LE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12
-; MM-MNO-BE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12
-; MM-MNO-PIC-DAG: lw $[[R4:[0-9]+]], %got(g0)($[[R2]])
-; MM-MNO-PIC-DAG: sw16 $[[R3]], 0($[[R4]])
-; MM-MNO-LE-PIC-DAG: mfhc1 $[[R5:[0-9]+]], $f12
-; MM-MNO-BE-PIC-DAG: mfc1 $[[R5:[0-9]+]], $f12
-; MM-MNO-PIC-DAG: sw16 $[[R5]], 4($[[R4]])
+; MM-MNO-LE-PIC: mfc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfhc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-PIC: lw $[[R4:[0-9]+]], %got(g0)($[[R2]])
+; MM-MNO-PIC: sw16 $[[R3]], 0($[[R4]])
+; MM-MNO-LE-PIC: mfhc1 $[[R5:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfc1 $[[R5:[0-9]+]], $f12
+; MM-MNO-PIC: sw16 $[[R5]], 4($[[R4]])
; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0)
; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]])
@@ -267,8 +267,8 @@
; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3
; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]]
-; MM-MNO-PIC-DAG: lw16 $[[R2:[0-9]+]], 0($[[R1]])
-; MM-MNO-PIC-DAG: lw16 $[[R3:[0-9]+]], 4($[[R1]])
+; MM-MNO-PIC: lw16 $[[R2:[0-9]+]], 0($[[R1]])
+; MM-MNO-PIC: lw16 $[[R3:[0-9]+]], 4($[[R1]])
; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0
; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0
; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0
@@ -313,14 +313,14 @@
; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
; MM: sdc1 $f12, 0($[[R1]])
-; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3
-; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
-; MM-MNO-LE-PIC-DAG: mfc1 $[[R2:[0-9]+]], $f12
-; MM-MNO-BE-PIC-DAG: mfhc1 $[[R2:[0-9]+]], $f12
-; MM-MNO-PIC-DAG: sw16 $[[R2]], 0($[[R1]])
-; MM-MNO-LE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12
-; MM-MNO-BE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12
-; MM-MNO-PIC-DAG: sw16 $[[R3]], 4($[[R1]])
+; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3
+; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
+; MM-MNO-LE-PIC: mfc1 $[[R2:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfhc1 $[[R2:[0-9]+]], $f12
+; MM-MNO-PIC: sw16 $[[R2]], 0($[[R1]])
+; MM-MNO-LE-PIC: mfhc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfc1 $[[R3:[0-9]+]], $f12
+; MM-MNO-PIC: sw16 $[[R3]], 4($[[R1]])
; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3
; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]
diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
index ac69dc9..9957d5b 100644
--- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
@@ -234,15 +234,15 @@
; MIPS32: insert.w $w[[W0]][1], $[[R1]]
; MIPS32: insert.w $w[[W0]][3], $[[R1]]
-; MIPS64-N64-DAG: ld $[[R3:[0-9]+]], %got_disp(h)
-; MIPS64-N32-DAG: lw $[[R3:[0-9]+]], %got_disp(h)
-; MIPS64-DAG: dmfc1 $[[R1:[0-9]+]], $f[[F2]]
-; MIPS64-DAG: fill.d $w[[W0:[0-9]+]], $[[R1]]
+; MIPS64-N64: ld $[[R3:[0-9]+]], %got_disp(h)
+; MIPS64-N32: lw $[[R3:[0-9]+]], %got_disp(h)
+; MIPS64: dmfc1 $[[R1:[0-9]+]], $f[[F2]]
+; MIPS64: fill.d $w[[W0:[0-9]+]], $[[R1]]
-; ALL-DAG: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]]
-; ALL-DAG: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]]
+; ALL: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]]
+; ALL: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]]
-; MIPS32-DAG: lw $[[R3:[0-9]+]], %got(h)
+; MIPS32: lw $[[R3:[0-9]+]], %got(h)
; ALL: copy_u.h $[[R2:[0-9]+]], $w[[W2]]
; ALL: sh $[[R2]], 0($[[R3]])
diff --git a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
index 812c400..c644d24 100644
--- a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
@@ -336,8 +336,8 @@
; CHECK: llvm_mips_st_b_valid_range_tests:
; CHECK: ld.b
-; CHECK-DAG: st.b [[R1:\$w[0-9]+]], -512(
-; CHECK-DAG: st.b [[R1:\$w[0-9]+]], 511(
+; CHECK: st.b [[R1:\$w[0-9]+]], -512(
+; CHECK: st.b [[R1:\$w[0-9]+]], 511(
; CHECK: .size llvm_mips_st_b_valid_range_tests
;
@@ -351,10 +351,10 @@
}
; CHECK: llvm_mips_st_b_invalid_range_tests:
-; CHECK: addiu $2, $1, 512
+; CHECK: addiu $2, $1, -513
; CHECK: ld.b
; CHECK: st.b [[R1:\$w[0-9]+]], 0(
-; CHECK: addiu $1, $1, -513
+; CHECK: addiu $1, $1, 512
; CHECK: st.b [[R1:\$w[0-9]+]], 0(
; CHECK: .size llvm_mips_st_b_invalid_range_tests
;
@@ -404,8 +404,8 @@
; CHECK: llvm_mips_st_h_valid_range_tests:
; CHECK: ld.h
-; CHECK-DAG: st.h [[R1:\$w[0-9]+]], -1024(
-; CHECK-DAG: st.h [[R1:\$w[0-9]+]], 1022(
+; CHECK: st.h [[R1:\$w[0-9]+]], -1024(
+; CHECK: st.h [[R1:\$w[0-9]+]], 1022(
; CHECK: .size llvm_mips_st_h_valid_range_tests
;
@@ -419,10 +419,10 @@
}
; CHECK: llvm_mips_st_h_invalid_range_tests:
-; CHECK: addiu $2, $1, 1024
+; CHECK: addiu $2, $1, -1026
; CHECK: ld.h
; CHECK: st.h [[R1:\$w[0-9]+]], 0(
-; CHECK: addiu $1, $1, -1026
+; CHECK: addiu $1, $1, 1024
; CHECK: st.h [[R1:\$w[0-9]+]], 0(
; CHECK: .size llvm_mips_st_h_invalid_range_tests
;
@@ -472,8 +472,8 @@
; CHECK: llvm_mips_st_w_valid_range_tests:
; CHECK: ld.w
-; CHECK-DAG: st.w [[R1:\$w[0-9]+]], -2048(
-; CHECK-DAG: st.w [[R1:\$w[0-9]+]], 2044(
+; CHECK: st.w [[R1:\$w[0-9]+]], -2048(
+; CHECK: st.w [[R1:\$w[0-9]+]], 2044(
; CHECK: .size llvm_mips_st_w_valid_range_tests
;
@@ -487,10 +487,10 @@
}
; CHECK: llvm_mips_st_w_invalid_range_tests:
-; CHECK: addiu $2, $1, 2048
+; CHECK: addiu $2, $1, -2052
; CHECK: ld.w
; CHECK: st.w [[R1:\$w[0-9]+]], 0(
-; CHECK: addiu $1, $1, -2052
+; CHECK: addiu $1, $1, 2048
; CHECK: st.w [[R1:\$w[0-9]+]], 0(
; CHECK: .size llvm_mips_st_w_invalid_range_tests
;
@@ -540,8 +540,8 @@
; CHECK: llvm_mips_st_d_valid_range_tests:
; CHECK: ld.d
-; CHECK-DAG: st.d [[R1:\$w[0-9]+]], -4096(
-; CHECK-DAG: st.d [[R1:\$w[0-9]+]], 4088(
+; CHECK: st.d [[R1:\$w[0-9]+]], -4096(
+; CHECK: st.d [[R1:\$w[0-9]+]], 4088(
; CHECK: .size llvm_mips_st_d_valid_range_tests
;
@@ -555,10 +555,10 @@
}
; CHECK: llvm_mips_st_d_invalid_range_tests:
-; CHECK: addiu $2, $1, 4096
+; CHECK: addiu $2, $1, -4104
; CHECK: ld.d
; CHECK: st.d [[R1:\$w[0-9]+]], 0(
-; CHECK: addiu $1, $1, -4104
+; CHECK: addiu $1, $1, 4096
; CHECK: st.d [[R1:\$w[0-9]+]], 0(
; CHECK: .size llvm_mips_st_d_invalid_range_tests
;
diff --git a/llvm/test/CodeGen/Mips/o32_cc_byval.ll b/llvm/test/CodeGen/Mips/o32_cc_byval.ll
index eadf4ab..33431db 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_byval.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_byval.ll
@@ -45,18 +45,20 @@
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry:
; CHECK: addiu $sp, $sp, -48
-; CHECK-DAG: sw $7, 60($sp)
-; CHECK-DAG: sw $6, 56($sp)
-; CHECK-DAG: ldc1 $f[[F0:[0-9]+]], 72($sp)
-; CHECK-DAG: lw $[[R3:[0-9]+]], 64($sp)
-; CHECK-DAG: lw $[[R4:[0-9]+]], 68($sp)
-; CHECK-DAG: lh $[[R1:[0-9]+]], 58($sp)
-; CHECK-DAG: lb $[[R0:[0-9]+]], 56($sp)
-; CHECK-DAG: sw $[[R0]], 32($sp)
-; CHECK-DAG: sw $[[R1]], 28($sp)
-; CHECK-DAG: sw $[[R4]], 20($sp)
-; CHECK-DAG: sw $[[R3]], 16($sp)
-; CHECK-DAG: sw $7, 24($sp)
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: lw $4, 80($sp)
+; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp)
+; CHECK: lw $[[R3:[0-9]+]], 64($sp)
+; CHECK: lw $[[R4:[0-9]+]], 68($sp)
+; CHECK: lw $[[R2:[0-9]+]], 60($sp)
+; CHECK: lh $[[R1:[0-9]+]], 58($sp)
+; CHECK: lb $[[R0:[0-9]+]], 56($sp)
+; CHECK: sw $[[R0]], 32($sp)
+; CHECK: sw $[[R1]], 28($sp)
+; CHECK: sw $[[R2]], 24($sp)
+; CHECK: sw $[[R4]], 20($sp)
+; CHECK: sw $[[R3]], 16($sp)
; CHECK: mfc1 $6, $f[[F0]]
%i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5
@@ -80,11 +82,13 @@
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry:
; CHECK: addiu $sp, $sp, -48
-; CHECK-DAG: sw $7, 60($sp)
-; CHECK-DAG: sw $6, 56($sp)
-; CHECK-DAG: sw $5, 52($sp)
-; CHECK-DAG: sw $4, 48($sp)
-; CHECK-DAG: sw $7, 24($sp)
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: sw $5, 52($sp)
+; CHECK: sw $4, 48($sp)
+; CHECK: lw $4, 48($sp)
+; CHECK: lw $[[R0:[0-9]+]], 60($sp)
+; CHECK: sw $[[R0]], 24($sp)
%arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 0
%tmp = load i32, i32* %arrayidx, align 4
@@ -97,14 +101,14 @@
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry:
; CHECK: addiu $sp, $sp, -48
-; CHECK-DAG: sw $7, 60($sp)
-; CHECK-DAG: sw $6, 56($sp)
-; CHECK-DAG: sw $5, 52($sp)
-; CHECK-DAG: lw $[[R1:[0-9]+]], 80($sp)
-; CHECK-DAG: lb $[[R0:[0-9]+]], 52($sp)
-; CHECK-DAG: sw $[[R0]], 32($sp)
-; CHECK-DAG: sw $[[R1]], 24($sp)
-; CHECK: move $4, $7
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: sw $5, 52($sp)
+; CHECK: lw $4, 60($sp)
+; CHECK: lw $[[R1:[0-9]+]], 80($sp)
+; CHECK: lb $[[R0:[0-9]+]], 52($sp)
+; CHECK: sw $[[R0]], 32($sp)
+; CHECK: sw $[[R1]], 24($sp)
%i = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 2
%tmp = load i32, i32* %i, align 4
diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
index 73aad48..1dc3a92 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -29,9 +29,9 @@
; CHECK-LABEL: va1:
; CHECK: addiu $sp, $sp, -16
-; CHECK: sw $5, 20($sp)
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
; CHECK: lw $2, 20($sp)
}
@@ -83,8 +83,8 @@
; CHECK-LABEL: va3:
; CHECK: addiu $sp, $sp, -16
-; CHECK: sw $6, 24($sp)
; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
; CHECK: lw $2, 24($sp)
}