AArch64 & ARM: remove undefined behaviour from some tests.
llvm-svn: 209880
diff --git a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
index 35995b7..b040b2d 100644
--- a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
@@ -4,22 +4,26 @@
%struct.foo = type { i64, i64 }
-define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
+define zeroext i8 @t(%struct.foo* %this, i1 %tst) noreturn optsize {
entry:
; ARM-LABEL: t:
-; ARM: str r2, [r1], r0
+; ARM-DAG: mov r[[ADDR:[0-9]+]], #8
+; ARM-DAG: mov [[VAL:r[0-9]+]], #0
+; ARM: str [[VAL]], [r[[ADDR]]], r0
; THUMB-LABEL: t:
-; THUMB-NOT: str r0, [r1], r0
-; THUMB: str r1, [r0]
+; THUMB-DAG: movs r[[ADDR:[0-9]+]], #8
+; THUMB-DAG: movs [[VAL:r[0-9]+]], #0
+; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}}
+; THUMB: str [[VAL]], [r[[ADDR]]]
%0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
store i32 0, i32* inttoptr (i32 8 to i32*), align 8
- br i1 undef, label %bb.nph96, label %bb3
+ br i1 %tst, label %bb.nph96, label %bb3
bb3: ; preds = %entry
%1 = load i64* %0, align 4 ; <i64> [#uses=0]
- unreachable
+ ret i8 42
bb.nph96: ; preds = %entry
- unreachable
+ ret i8 3
}
diff --git a/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll b/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
index 32d350e9..6037998 100644
--- a/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
+++ b/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
@@ -11,7 +11,7 @@
define i32 @test(i32 %x) {
entry:
%0 = tail call signext i16 undef(i32* undef)
- switch i32 undef, label %bb3 [
+ switch i32 %x, label %bb3 [
i32 0, label %bb4
i32 1, label %bb1
i32 2, label %bb2
diff --git a/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll b/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
index 85a1137..1bbb7b4 100644
--- a/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
+++ b/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
@@ -7,7 +7,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
target triple = "armv6-apple-darwin10"
-define void @ptoa() nounwind {
+define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind {
entry:
br i1 false, label %bb3, label %bb
@@ -16,7 +16,7 @@
bb3: ; preds = %bb, %entry
%0 = call noalias i8* @malloc() nounwind
- br i1 undef, label %bb46, label %bb8
+ br i1 %tst, label %bb46, label %bb8
bb8: ; preds = %bb3
%1 = getelementptr inbounds i8* %0, i32 0
@@ -35,7 +35,7 @@
%7 = or i8 %6, 48
%8 = add i8 %6, 87
%iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8
- store i8 %iftmp.5.0.1, i8* undef, align 1
+ store i8 %iftmp.5.0.1, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@@ -49,7 +49,7 @@
%13 = or i8 %12, 48
%14 = add i8 %12, 87
%iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14
- store i8 %iftmp.5.0.2, i8* undef, align 1
+ store i8 %iftmp.5.0.2, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@@ -73,8 +73,8 @@
%21 = udiv i32 %2, 100000
%22 = urem i32 %21, 10
%23 = icmp ult i32 %22, 10
- %iftmp.5.0.5 = select i1 %23, i8 0, i8 undef
- store i8 %iftmp.5.0.5, i8* undef, align 1
+ %iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8
+ store i8 %iftmp.5.0.5, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@@ -88,7 +88,7 @@
%28 = or i8 %27, 48
%29 = add i8 %27, 87
%iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29
- store i8 %iftmp.5.0.6, i8* undef, align 1
+ store i8 %iftmp.5.0.6, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@@ -102,7 +102,7 @@
%34 = or i8 %33, 48
%35 = add i8 %33, 87
%iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35
- store i8 %iftmp.5.0.7, i8* undef, align 1
+ store i8 %iftmp.5.0.7, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@@ -117,7 +117,7 @@
%41 = add i8 %39, 87
%iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41
store i8 %iftmp.5.0.8, i8* null, align 1
- unreachable
+ br label %bb46
bb46: ; preds = %bb3
ret void
diff --git a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
index bc72e12..837feb6 100644
--- a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
+++ b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
@@ -8,7 +8,7 @@
@oStruct = external global %struct.Outer, align 4
-define void @main() nounwind {
+define void @main(i8 %val8) nounwind {
; CHECK-LABEL: main:
; CHECK-NOT: ldrd
; CHECK: mul
@@ -28,7 +28,7 @@
br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16
if.then.i16: ; preds = %_Z14printIsNotZeroi.exit
- unreachable
+ ret void
_Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi.exit
br label %_Z14printIsNotZeroi.exit17.for.body_crit_edge
@@ -36,7 +36,7 @@
_Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17
%b.phi.trans.insert = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3
%tmp3.pre = load i8* %b.phi.trans.insert, align 1
- %phitmp27 = icmp eq i8 undef, 0
+ %phitmp27 = icmp eq i8 %val8, 0
br label %for.body
for.end: ; preds = %_Z14printIsNotZeroi.exit17
diff --git a/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
index 480d087..162f863 100644
--- a/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
@@ -42,34 +42,34 @@
ret i32 %tmp13
}
-define hidden fastcc void @t3(i8** %retaddr) {
+define hidden fastcc void @t3(i8** %retaddr, i1 %tst, i8* %p8) {
; CHECK-LABEL: t3:
; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen
bb:
store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr
- br i1 undef, label %bb77, label %bb7.i
+ br i1 %tst, label %bb77, label %bb7.i
bb7.i: ; preds = %bb35
br label %bb2.i
KBBlockZero_return_1: ; preds = %KBBlockZero.exit
- unreachable
+ ret void
KBBlockZero_return_0: ; preds = %KBBlockZero.exit
- unreachable
+ ret void
bb77: ; preds = %bb26, %bb12, %bb
ret void
bb2.i: ; preds = %bb6.i350, %bb7.i
- br i1 undef, label %bb6.i350, label %KBBlockZero.exit
+ br i1 %tst, label %bb6.i350, label %KBBlockZero.exit
bb6.i350: ; preds = %bb2.i
br label %bb2.i
KBBlockZero.exit: ; preds = %bb2.i
- indirectbr i8* undef, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
+ indirectbr i8* %p8, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
}
@foo = global i32 ()* null
diff --git a/llvm/test/CodeGen/ARM/va_arg.ll b/llvm/test/CodeGen/ARM/va_arg.ll
index f18b498..d901a74 100644
--- a/llvm/test/CodeGen/ARM/va_arg.ll
+++ b/llvm/test/CodeGen/ARM/va_arg.ll
@@ -24,13 +24,13 @@
; CHECK-NOT: bfc
; CHECK: bx lr
-define double @test2(i32 %a, i32 %b, ...) nounwind optsize {
+define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
entry:
%ap = alloca i8*, align 4 ; <i8**> [#uses=3]
%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
call void @llvm.va_start(i8* %ap1)
%0 = va_arg i8** %ap, i32 ; <i32> [#uses=0]
- store i32 %0, i32* undef
+ store i32 %0, i32* %b
%1 = va_arg i8** %ap, double ; <double> [#uses=1]
call void @llvm.va_end(i8* %ap1)
ret double %1
diff --git a/llvm/test/CodeGen/ARM/widen-vmovs.ll b/llvm/test/CodeGen/ARM/widen-vmovs.ll
index 1efbc73..316cfab 100644
--- a/llvm/test/CodeGen/ARM/widen-vmovs.ll
+++ b/llvm/test/CodeGen/ARM/widen-vmovs.ll
@@ -17,7 +17,7 @@
; - Register liveness is verified.
; - The execution domain switch to vorr works across basic blocks.
-define void @Mm() nounwind {
+define void @Mm(i32 %in, float* %addr) nounwind {
entry:
br label %for.body4
@@ -27,10 +27,10 @@
for.body.i:
%tmp3.i = phi float [ 1.000000e+10, %for.body4 ], [ %add.i, %for.body.i ]
%add.i = fadd float %tmp3.i, 1.000000e+10
- %exitcond.i = icmp eq i32 undef, 41
+ %exitcond.i = icmp eq i32 %in, 41
br i1 %exitcond.i, label %rInnerproduct.exit, label %for.body.i
rInnerproduct.exit:
- store float %add.i, float* undef, align 4
+ store float %add.i, float* %addr, align 4
br label %for.body4
}