commit cee607e4144e6391472e04235479969d9b0408a2
author Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Wed Apr 24 17:03:15 2019 +0000
committer Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Wed Apr 24 17:03:15 2019 +0000
tree c8d40338463d9de3eeee008a50bb8e408cac584b
parent c60a4099a15ad83b19e5389284e1186a7dddd591

[AMDGPU] Add gfx1010 target definitions

Differential Revision: https://reviews.llvm.org/D61041

llvm-svn: 359113

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 19af9d3..52e5ab5 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -999,6 +999,10 @@
     return AMDGPU::isGFX9(getSTI());
   }
 
+  bool isGFX10() const {
+    return AMDGPU::isGFX10(getSTI());
+  }
+
   bool hasInv2PiInlineImm() const {
     return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
   }
@@ -1407,7 +1411,7 @@
 bool AMDGPUOperand::isSDWAOperand(MVT type) const {
   if (AsmParser->isVI())
     return isVReg32();
-  else if (AsmParser->isGFX9())
+  else if (AsmParser->isGFX9() || AsmParser->isGFX10())
     return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type);
   else
     return false;
@@ -2953,7 +2957,7 @@
   if (getParser().parseIdentifier(KernelName))
     return true;
 
-  kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor();
+  kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());
 
   StringSet<> Seen;