[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX10;
- added description of operands sccz, vccz, lds_direct, etc;
- minor bugfixing and improvements.
llvm-svn: 365347
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
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+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+============================
+Syntax of GFX10 Instructions
+============================
+
+.. contents::
+ :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DPP16
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+
+DPP8
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid10_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid10_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop
+ ds_or_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata128_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata96_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ exp :ref:`tgt<amdgpu_synid10_tgt>`, :ref:`vsrc0<amdgpu_synid10_src_exp>`, :ref:`vsrc1<amdgpu_synid10_src_exp>`, :ref:`vsrc2<amdgpu_synid10_src_exp>`, :ref:`vsrc3<amdgpu_synid10_src_exp>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f32x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`f64x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata96_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata128_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dword :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sshort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ushort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_byte :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dword :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_short :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_and :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid10_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_or :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_gather4 :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_get_lod :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_sample :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid10_data_mimg_store>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_store_pck :ref:`vdata<amdgpu_synid10_data_mimg_store>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_gl0_inv
+ buffer_gl1_inv
+ buffer_load_dword :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+SDWA
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sub_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+SMEM
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`imm3<amdgpu_synid10_perm_smem>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+ s_atc_probe_buffer :ref:`imm3<amdgpu_synid10_perm_smem>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>`
+ s_atomic_add :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid10_sdst512_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid10_sdst128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid10_sdst256_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid10_sdata32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid10_sdata64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid10_sdata128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+ s_dcache_inv
+ s_dcache_wb
+ s_get_waveid_in_workgroup :ref:`sdst<amdgpu_synid10_sdst32_0>`
+ s_gl1_inv
+ s_load_dword :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid10_sdst512_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid10_sdst128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid10_sdst256_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid10_sdst64_0>`
+ s_memtime :ref:`sdst<amdgpu_synid10_sdst64_0>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid10_sdst128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid10_sdata32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid10_sdata64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid10_sdata128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid10_sdata32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid10_sdata64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid10_sdata128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_and_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn1_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn1_wrexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn2_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn2_wrexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_1>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_movrelsd_2_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_1>`
+ s_nand_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_nor_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_not_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_not_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_or_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_orn1_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_orn2_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_xnor_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_xor_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_absdiff_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_add_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_and_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_and_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_max_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_max_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_min_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_min_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_or_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_or_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_call_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`label<amdgpu_synid10_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`hwreg<amdgpu_synid10_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid10_hwreg>`, :ref:`ssrc<amdgpu_synid10_ssrc32_2>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid10_hwreg>`, :ref:`imm32<amdgpu_synid10_bimm32>`
+ s_subvector_loop_begin :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`label<amdgpu_synid10_label>`
+ s_subvector_loop_end :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`label<amdgpu_synid10_label>`
+ s_version :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_expcnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_lgkmcnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_vmcnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_vscnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid10_label>`
+ s_clause :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_code_end
+ s_decperflevel :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_denorm_mode :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_endpgm
+ s_endpgm_ordered_ps_done
+ s_endpgm_saved
+ s_icache_inv
+ s_incperflevel :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_inst_prefetch :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_nop :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_round_mode :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_sendmsg :ref:`msg<amdgpu_synid10_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid10_msg>`
+ s_sethalt :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_setkill :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_setprio :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_sleep :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_trap :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_ttracedata
+ s_ttracedata_imm :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt :ref:`waitcnt<amdgpu_synid10_waitcnt>`
+ s_wakeup
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`param<amdgpu_synid10_param>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_clrexcp
+ v_cos_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_log_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_log_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movreld_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movrels_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_2_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_pipeflush
+ v_rcp_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid10_sdst32_2>`, :ref:`vsrc<amdgpu_synid10_vsrc32_1>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_swaprel_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_add_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_add_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_add_nc_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_and_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_fmaak_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`imm32<amdgpu_synid10_fimm16>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`imm32<amdgpu_synid10_fimm32>`
+ v_fmac_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_fmamk_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`imm32<amdgpu_synid10_fimm16>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`imm32<amdgpu_synid10_fimm32>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mac_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mac_legacy_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_madak_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`imm32<amdgpu_synid10_fimm32>`
+ v_madmk_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`imm32<amdgpu_synid10_fimm32>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+ v_max_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_max_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_max_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_max_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_or_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_sub_co_ci_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_sub_nc_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_subrev_co_ci_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_subrev_nc_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_add_co_ci_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_co_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_add_nc_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_add_nc_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_clrexcp_e64
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_eq_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_eq_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_f_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_f_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_f_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_f_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ge_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ge_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_gt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_gt_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_le_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_le_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_lg_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_lt_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ne_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ne_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_neq_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_t_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_t_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_t_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_tru_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`, :ref:`src2<amdgpu_synid10_src64_0>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid10_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p2_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`i64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_max_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_min_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movrels_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_2_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b128<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`vsrc2<amdgpu_synid10_vsrc128_0>`::ref:`b128<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mullit_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_nop_e64
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_permlane16_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`, :ref:`ssrc2<amdgpu_synid10_ssrc32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_permlanex16_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`, :ref:`ssrc2<amdgpu_synid10_ssrc32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_pipeflush_e64
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid10_sdst32_2>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_ci_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_nc_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_sub_nc_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_nc_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_5>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_xor3_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+
+VOP3P
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_class_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_eq_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_eq_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_eq_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_f_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_f_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_f_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ge_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ge_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ge_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_gt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_gt_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_gt_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_le_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_le_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_le_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lg_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lg_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lg_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lt_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lt_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ne_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ne_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_neq_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_neq_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_neq_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nge_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nge_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nge_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ngt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ngt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ngt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nle_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nle_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nle_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nlg_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlg_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlg_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nlt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_o_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_o_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_o_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_t_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_t_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_t_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_t_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_tru_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_tru_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_tru_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_u_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_u_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_u_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+ :hidden:
+
+ gfx10_attr
+ gfx10_bimm16
+ gfx10_bimm32
+ gfx10_fimm16
+ gfx10_fimm32
+ gfx10_hwreg
+ gfx10_label
+ gfx10_msg
+ gfx10_param
+ gfx10_perm_smem
+ gfx10_simm16
+ gfx10_tgt
+ gfx10_uimm16
+ gfx10_vcc_32
+ gfx10_waitcnt
+ gfx10_addr_buf
+ gfx10_addr_ds
+ gfx10_addr_flat
+ gfx10_addr_mimg
+ gfx10_base_smem_addr
+ gfx10_base_smem_buf
+ gfx10_base_smem_scratch
+ gfx10_data_buf_atomic128
+ gfx10_data_buf_atomic32
+ gfx10_data_buf_atomic64
+ gfx10_data_mimg_atomic_cmp
+ gfx10_data_mimg_atomic_reg
+ gfx10_data_mimg_store
+ gfx10_data_mimg_store_d16
+ gfx10_data_smem_atomic128
+ gfx10_data_smem_atomic32
+ gfx10_data_smem_atomic64
+ gfx10_dst_buf_128
+ gfx10_dst_buf_32
+ gfx10_dst_buf_64
+ gfx10_dst_buf_96
+ gfx10_dst_buf_lds
+ gfx10_dst_flat_atomic32
+ gfx10_dst_flat_atomic64
+ gfx10_dst_mimg_gather4
+ gfx10_dst_mimg_regular
+ gfx10_dst_mimg_regular_d16
+ gfx10_offset_buf
+ gfx10_offset_smem_buf
+ gfx10_offset_smem_plain
+ gfx10_rsrc_buf
+ gfx10_rsrc_mimg
+ gfx10_saddr_flat_global
+ gfx10_saddr_flat_scratch
+ gfx10_samp_mimg
+ gfx10_sdata128_0
+ gfx10_sdata32_0
+ gfx10_sdata64_0
+ gfx10_sdst128_0
+ gfx10_sdst256_0
+ gfx10_sdst32_0
+ gfx10_sdst32_1
+ gfx10_sdst32_2
+ gfx10_sdst512_0
+ gfx10_sdst64_0
+ gfx10_sdst64_1
+ gfx10_src32_0
+ gfx10_src32_1
+ gfx10_src32_2
+ gfx10_src32_3
+ gfx10_src64_0
+ gfx10_src_exp
+ gfx10_ssrc32_0
+ gfx10_ssrc32_1
+ gfx10_ssrc32_2
+ gfx10_ssrc32_3
+ gfx10_ssrc32_4
+ gfx10_ssrc32_5
+ gfx10_ssrc64_0
+ gfx10_ssrc64_1
+ gfx10_vaddr_flat_global
+ gfx10_vaddr_flat_scratch
+ gfx10_vdata128_0
+ gfx10_vdata32_0
+ gfx10_vdata64_0
+ gfx10_vdata96_0
+ gfx10_vdst128_0
+ gfx10_vdst32_0
+ gfx10_vdst64_0
+ gfx10_vdst96_0
+ gfx10_vsrc128_0
+ gfx10_vsrc32_0
+ gfx10_vsrc32_1
+ gfx10_vsrc64_0
+ gfx10_wsdst
+ gfx10_wssrc
+ gfx10_mad_type_dev
+ gfx10_mod_dpp_sdwa_abs_neg
+ gfx10_mod_sdwa_sext
+ gfx10_mod_vop3_abs_neg
+ gfx10_opt
+ gfx10_ret
+ gfx10_type_dev
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
index b267149..1933aff 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
@@ -188,7 +188,7 @@
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
flat_atomic_add :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_add_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_and :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@@ -555,22 +555,22 @@
s_addk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
s_cbranch_i_fork :ref:`ssrc<amdgpu_synid7_ssrc64_3>`, :ref:`label<amdgpu_synid7_label>`
s_cmovk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_uimm16>`
- s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_uimm16>`
- s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_uimm16>`
- s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_uimm16>`
- s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_uimm16>`
- s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_1>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
s_getreg_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`hwreg<amdgpu_synid7_hwreg>`
s_movk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
s_mulk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
- s_setreg_b32 :ref:`hwreg<amdgpu_synid7_hwreg>`, :ref:`ssrc<amdgpu_synid7_ssrc32_1>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid7_hwreg>`, :ref:`ssrc<amdgpu_synid7_ssrc32_4>`
s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid7_hwreg>`, :ref:`imm32<amdgpu_synid7_bimm32>`
SOPP
@@ -678,7 +678,7 @@
v_rcp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
v_rcp_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
- v_readfirstlane_b32 :ref:`sdst<amdgpu_synid7_sdst32_2>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid7_sdst32_2>`, :ref:`vsrc<amdgpu_synid7_vsrc32_1>`
v_rndne_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
v_rndne_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
v_rsq_clamp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
@@ -704,7 +704,7 @@
v_addc_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
v_and_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_ashr_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_bfm_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_cndmask_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
@@ -716,9 +716,9 @@
v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_ldexp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`i32<amdgpu_synid7_type_dev>`
v_lshl_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_lshr_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_mac_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_mac_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_madak_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`imm32<amdgpu_synid7_fimm32>`
@@ -740,14 +740,14 @@
v_mul_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_mul_u32_u24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_or_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
- v_readlane_b32 :ref:`sdst<amdgpu_synid7_sdst32_2>`, :ref:`vsrc0<amdgpu_synid7_vsrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_4>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid7_sdst32_2>`, :ref:`vsrc0<amdgpu_synid7_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_5>`
v_sub_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_sub_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
v_subb_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
- v_subbrev_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
- v_subrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
- v_writelane_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_4>`
+ v_subbrev_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_subrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_6>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_5>`
v_xor_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
VOP3
@@ -757,369 +757,369 @@
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_add_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_addc_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
- v_alignbit_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_alignbyte_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_and_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_ashr_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_ashr_i64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_bcnt_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_bfe_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_bfe_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_bfi_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_bfm_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_ceil_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_addc_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_ashr_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_ashr_i64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_bcnt_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_bfm_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_ceil_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_clrexcp_e64
- v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
- v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
- v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmps_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmps_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpsx_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpsx_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
- v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
- v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
- v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
- v_cos_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_5>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_cvt_pk_u16_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_cvt_pkaccum_u8_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_cvt_pknorm_i16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_pknorm_u16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
- v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cvt_pk_u16_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_cvt_pkaccum_u8_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_cvt_pknorm_i16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_pknorm_u16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_div_fixup_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_div_fixup_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_div_fmas_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
v_div_scale_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`, :ref:`src2<amdgpu_synid7_src64_1>`
- v_exp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_floor_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_floor_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_fma_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_fract_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
- v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`
- v_log_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshl_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_lshl_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_lshr_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_lshr_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mac_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i32_i24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`
- v_mad_i64_i32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`i64<amdgpu_synid7_type_dev>`
- v_mad_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u32_u24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_mad_u64_u32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`u64<amdgpu_synid7_type_dev>`
- v_max3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_max3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_max_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_log_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshl_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_lshr_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshr_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`i64<amdgpu_synid7_type_dev>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`u64<amdgpu_synid7_type_dev>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_max_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_max_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mbcnt_hi_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mbcnt_lo_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_med3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_med3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_min3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_min3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_min_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_max_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mbcnt_hi_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mbcnt_lo_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_min_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_min_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mov_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_movreld_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_min_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
v_movrels_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
- v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
- v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b128<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`vsrc2<amdgpu_synid7_vsrc128_0>`::ref:`b128<amdgpu_synid7_type_dev>`
- v_msad_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`
- v_mul_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b128<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`vsrc2<amdgpu_synid7_vsrc128_0>`::ref:`b128<amdgpu_synid7_type_dev>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_mul_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_hi_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_lo_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_mullit_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mullit_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_nop_e64
- v_not_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`
- v_or_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
- v_rcp_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+ v_rcp_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rcp_clamp_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rcp_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rndne_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rsq_clamp_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rsq_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_sad_u16 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_sad_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`src2<amdgpu_synid7_src32_2>`
- v_sad_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
- v_sin_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_subb_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
- v_subbrev_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
- v_subrev_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
- v_trig_preop_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_subb_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_subbrev_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_4>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_4>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_trunc_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_xor_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`src1<amdgpu_synid7_src32_2>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
VOPC
-----------------------
@@ -1380,6 +1380,9 @@
gfx7_src32_1
gfx7_src32_2
gfx7_src32_3
+ gfx7_src32_4
+ gfx7_src32_5
+ gfx7_src32_6
gfx7_src64_0
gfx7_src64_1
gfx7_src64_2
@@ -1389,6 +1392,8 @@
gfx7_ssrc32_2
gfx7_ssrc32_3
gfx7_ssrc32_4
+ gfx7_ssrc32_5
+ gfx7_ssrc32_6
gfx7_ssrc64_0
gfx7_ssrc64_1
gfx7_ssrc64_2
@@ -1404,6 +1409,7 @@
gfx7_vdst96_0
gfx7_vsrc128_0
gfx7_vsrc32_0
+ gfx7_vsrc32_1
gfx7_vsrc64_0
gfx7_mod
gfx7_opt
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
index a6dbc9b..9c762aa 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
@@ -193,7 +193,7 @@
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
flat_atomic_add :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`, :ref:`vdata<amdgpu_synid8_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_add_x2 :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`, :ref:`vdata<amdgpu_synid8_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_and :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`, :ref:`vaddr<amdgpu_synid8_addr_flat>`, :ref:`vdata<amdgpu_synid8_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@@ -405,7 +405,7 @@
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_atc_probe :ref:`imm3<amdgpu_synid8_perm_smem>`, :ref:`sbase<amdgpu_synid8_base_smem_addr>`, :ref:`soffset<amdgpu_synid8_offset_smem_load>`
s_atc_probe_buffer :ref:`imm3<amdgpu_synid8_perm_smem>`, :ref:`sbase<amdgpu_synid8_base_smem_buf>`, :ref:`soffset<amdgpu_synid8_offset_smem_load>`
s_buffer_load_dword :ref:`sdst<amdgpu_synid8_sdst32_0>`, :ref:`sbase<amdgpu_synid8_base_smem_buf>`, :ref:`soffset<amdgpu_synid8_offset_smem_load>` :ref:`glc<amdgpu_synid_glc>`
@@ -805,7 +805,7 @@
v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_0>`
v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_readfirstlane_b32 :ref:`sdst<amdgpu_synid8_sdst32_2>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid8_sdst32_2>`, :ref:`vsrc<amdgpu_synid8_vsrc32_1>`
v_rndne_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_0>`
v_rndne_f16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -866,10 +866,10 @@
v_and_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_and_b32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_and_b32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_cndmask_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`
@@ -878,16 +878,16 @@
v_ldexp_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`
v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`i16<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_mac_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -978,19 +978,19 @@
v_subb_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`
v_subb_u32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subb_u32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid8_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subbrev_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`
+ v_subbrev_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`
v_subbrev_u32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subbrev_u32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid8_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_subrev_f16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_subrev_f32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_subrev_u16_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
v_subrev_u32_dpp :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_xor_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -1004,290 +1004,290 @@
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_add_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_add_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_addc_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
- v_alignbit_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_alignbyte_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_and_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_ashrrev_i64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_bfe_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
- v_bfe_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_bfi_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_bfm_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_ceil_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ceil_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_add_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_addc_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src64_1>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_ceil_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_clrexcp_e64
- v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
- v_cos_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cos_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
- v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
- v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_div_fixup_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_div_fixup_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_div_fmas_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
v_div_scale_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src64_1>`, :ref:`src1<amdgpu_synid8_src64_1>`, :ref:`src2<amdgpu_synid8_src64_1>`
- v_exp_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_exp_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_floor_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_floor_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_floor_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_fma_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fract_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_fract_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
- v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`param<amdgpu_synid8_param>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1295,116 +1295,116 @@
v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid8_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_interp_p2_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i16<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ldexp_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
- v_log_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_log_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_lshlrev_b64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_lshrrev_b64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src64_1>`
- v_mac_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mac_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i24 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i64_i32 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u24 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u64_u32 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_max3_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_max_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i16<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src64_1>`
+ v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src64_1>`
+ v_mac_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_max_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_max_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_max_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_max_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_med3_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_med3_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_min3_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_min3_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_min_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_min_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_max_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_min_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_min_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_min_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_min_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mov_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_movreld_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
+ v_min_i16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_min_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
v_movrels_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
- v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_msad_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_mul_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_hi_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_lo_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
v_nop_e64
- v_not_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`
- v_or_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_perm_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>`
- v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rcp_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_readlane_b32 :ref:`sdst<amdgpu_synid8_sdst32_2>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
- v_rndne_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rndne_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid8_sdst32_2>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rndne_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rsq_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rsq_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`src2<amdgpu_synid8_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sin_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sin_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`src2<amdgpu_synid8_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u8x4<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_sub_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_subb_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
- v_subbrev_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
- v_subrev_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_subrev_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
- v_trig_preop_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_trunc_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_sub_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subb_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subbrev_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_3>`, :ref:`src1<amdgpu_synid8_src32_3>`, :ref:`ssrc2<amdgpu_synid8_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_u16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`, :ref:`src1<amdgpu_synid8_src32_3>`
+ v_subrev_u32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`src0<amdgpu_synid8_src32_3>`, :ref:`src1<amdgpu_synid8_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_trunc_f64_e64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_writelane_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`ssrc0<amdgpu_synid8_ssrc32_4>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
- v_xor_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`, :ref:`src1<amdgpu_synid8_src32_1>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`, :ref:`src1<amdgpu_synid8_src32_3>`
VOPC
-----------------------
@@ -1814,6 +1814,8 @@
gfx8_sdst64_1
gfx8_src32_0
gfx8_src32_1
+ gfx8_src32_2
+ gfx8_src32_3
gfx8_src64_0
gfx8_src64_1
gfx8_src_exp
@@ -1837,6 +1839,7 @@
gfx8_vdst96_0
gfx8_vsrc128_0
gfx8_vsrc32_0
+ gfx8_vsrc32_1
gfx8_vsrc64_0
gfx8_mod_dpp_sdwa_abs_neg
gfx8_mod_sdwa_sext
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
index 9dd3b9d..3ffb9fd 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
@@ -501,7 +501,7 @@
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_atc_probe :ref:`imm3<amdgpu_synid9_perm_smem>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
s_atc_probe_buffer :ref:`imm3<amdgpu_synid9_perm_smem>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>`
s_atomic_add :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
@@ -980,7 +980,7 @@
v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_readfirstlane_b32 :ref:`sdst<amdgpu_synid9_sdst32_2>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid9_sdst32_2>`, :ref:`vsrc<amdgpu_synid9_vsrc32_1>`
v_rndne_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_rndne_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -1051,30 +1051,30 @@
v_and_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_and_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_and_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_cndmask_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_ldexp_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`
v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_mac_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_mac_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_mac_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
@@ -1164,24 +1164,24 @@
v_subb_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_subb_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subbrev_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
+ v_subbrev_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`
v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid9_vcc_64>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_subrev_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_subrev_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_subrev_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+ v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_subrev_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_xor_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
v_xor_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_xor_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1193,302 +1193,302 @@
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
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- v_add3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_add_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_add_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_add_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_add_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_add_lshl_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_add_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_add_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_addc_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
- v_alignbit_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_alignbyte_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_and_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_and_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_ashrrev_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_bfe_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
- v_bfe_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_bfi_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_bfm_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_ceil_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ceil_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_add_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_add_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_addc_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_ceil_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_clrexcp_e64
- v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
- v_cos_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cos_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
- v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
- v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_div_fixup_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fmas_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_div_fmas_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
v_div_scale_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src64_1>`, :ref:`src1<amdgpu_synid9_src64_1>`, :ref:`src2<amdgpu_synid9_src64_1>`
- v_exp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_exp_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_floor_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_floor_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_floor_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_fma_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fract_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fract_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_fract_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
- v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1497,138 +1497,138 @@
v_interp_p2_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_interp_p2_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_ldexp_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
- v_log_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_log_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshl_add_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_lshl_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_lshlrev_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_lshrrev_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
- v_mac_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mac_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i64_i32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_legacy_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u64_u32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_max3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_max3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_max3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_max_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i16<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
+ v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src64_1>`
+ v_mac_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_legacy_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_max_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_max_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_max_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_max_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_med3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_med3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_med3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_med3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_med3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_min3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_min3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_min3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_min3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_min3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_min_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_min_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_max_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_min_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_min_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_min_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_min_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mov_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_msad_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_min_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_mul_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_hi_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_lo_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
v_nop_e64
- v_not_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_or3_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_or_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_pack_b32_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_perm_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rcp_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_readlane_b32 :ref:`sdst<amdgpu_synid9_sdst32_2>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
- v_rndne_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rndne_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid9_sdst32_2>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rndne_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rsq_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_rsq_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`
- v_sin_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sin_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u8x4<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_sub_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_sub_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_sub_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_subb_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
- v_subbrev_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
- v_subrev_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_subrev_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_subrev_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
- v_trig_preop_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
- v_trunc_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_sub_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_sub_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subb_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subbrev_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`ssrc2<amdgpu_synid9_ssrc64_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_u16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`src1<amdgpu_synid9_src32_3>`
+ v_subrev_u32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_trunc_f64_e64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_writelane_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_4>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
- v_xad_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>`
- v_xor_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`
VOP3P
-----------------------
@@ -1637,28 +1637,28 @@
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_mad_mix_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_mixhi_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_mixlo_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_fma_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mad_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>`, :ref:`src2<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_max_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_min_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mul_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_sub_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_sub_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`, :ref:`src1<amdgpu_synid9_src32_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_mix_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_mixhi_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_mixlo_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>`, :ref:`src2<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_2>`, :ref:`src1<amdgpu_synid9_src32_3>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
VOPC
-----------------------
@@ -2067,6 +2067,8 @@
gfx9_sdst64_1
gfx9_src32_0
gfx9_src32_1
+ gfx9_src32_2
+ gfx9_src32_3
gfx9_src64_0
gfx9_src64_1
gfx9_src_exp
@@ -2092,6 +2094,7 @@
gfx9_vdst96_0
gfx9_vsrc128_0
gfx9_vsrc32_0
+ gfx9_vsrc32_1
gfx9_vsrc64_0
gfx9_mad_type_dev
gfx9_mod_dpp_sdwa_abs_neg
diff --git a/llvm/docs/AMDGPU/gfx10_addr_buf.rst b/llvm/docs/AMDGPU/gfx10_addr_buf.rst
new file mode 100644
index 0000000..bd57e9e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_buf.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_addr_buf:
+
+vaddr
+===========================
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_ds.rst b/llvm/docs/AMDGPU/gfx10_addr_ds.rst
new file mode 100644
index 0000000..b31862f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_ds.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_addr_ds:
+
+vaddr
+===========================
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_flat.rst b/llvm/docs/AMDGPU/gfx10_addr_flat.rst
new file mode 100644
index 0000000..cd780ca
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_flat.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_addr_flat:
+
+vaddr
+===========================
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_mimg.rst b/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
new file mode 100644
index 0000000..882fd8c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
@@ -0,0 +1,23 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_addr_mimg:
+
+vaddr
+===========================
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+
+* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_vcc_lo>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_attr.rst b/llvm/docs/AMDGPU/gfx10_attr.rst
new file mode 100644
index 0000000..f32f085
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_attr.rst
@@ -0,0 +1,30 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_attr:
+
+attr
+===========================
+
+Interpolation attribute and channel:
+
+ ============== ===================================
+ Syntax Description
+ ============== ===================================
+ attr{0..32}.x Attribute 0..32 with *x* channel.
+ attr{0..32}.y Attribute 0..32 with *y* channel.
+ attr{0..32}.z Attribute 0..32 with *z* channel.
+ attr{0..32}.w Attribute 0..32 with *w* channel.
+ ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+ v_interp_p1_f32 v1, v0, attr0.x
+ v_interp_p1_f32 v1, v0, attr32.w
+
diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst b/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst
new file mode 100644
index 0000000..9d52114
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_base_smem_addr:
+
+sbase
+===========================
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst
new file mode 100644
index 0000000..00e987d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_base_smem_buf:
+
+sbase
+===========================
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst b/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst
new file mode 100644
index 0000000..2b7e8b4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_base_smem_scratch:
+
+sbase
+===========================
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_bimm16.rst b/llvm/docs/AMDGPU/gfx10_bimm16.rst
new file mode 100644
index 0000000..00e9b71
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_bimm16.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_bimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_bimm32.rst b/llvm/docs/AMDGPU/gfx10_bimm32.rst
new file mode 100644
index 0000000..c4b87df
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_bimm32.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_bimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst b/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst
new file mode 100644
index 0000000..3ca9fb9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_buf_atomic128:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst
new file mode 100644
index 0000000..a8e6d9f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_buf_atomic32:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst b/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst
new file mode 100644
index 0000000..3840cd5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_buf_atomic64:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst
new file mode 100644
index 0000000..bd257cf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst
@@ -0,0 +1,27 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_mimg_atomic_cmp:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst
new file mode 100644
index 0000000..930dab3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_mimg_atomic_reg:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst
new file mode 100644
index 0000000..156c1b0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst
@@ -0,0 +1,18 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_mimg_store:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst
new file mode 100644
index 0000000..142b306
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_mimg_store_d16:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst
new file mode 100644
index 0000000..c59c488
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_smem_atomic128:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst
new file mode 100644
index 0000000..5e8f7ca
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_smem_atomic32:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
new file mode 100644
index 0000000..a8d5249
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_data_smem_atomic64:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst
new file mode 100644
index 0000000..56cfc2f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_buf_128:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst
new file mode 100644
index 0000000..a1f1dc9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_buf_32:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst
new file mode 100644
index 0000000..ebd3c7e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_buf_64:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst
new file mode 100644
index 0000000..13a7e2b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_buf_96:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst
new file mode 100644
index 0000000..ec83bf5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_buf_lds:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst
new file mode 100644
index 0000000..e8d94b8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_flat_atomic32:
+
+vdst
+===========================
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst
new file mode 100644
index 0000000..19d9b11
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_flat_atomic64:
+
+vdst
+===========================
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst b/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst
new file mode 100644
index 0000000..90b85935
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_mimg_gather4:
+
+vdst
+===========================
+
+Image data to load by an *image_gather4* instruction.
+
+*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+
+:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
+
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst
new file mode 100644
index 0000000..d337935
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_mimg_regular:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst
new file mode 100644
index 0000000..9217574
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_dst_mimg_regular_d16:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_fimm16.rst b/llvm/docs/AMDGPU/gfx10_fimm16.rst
new file mode 100644
index 0000000..c4d85be
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_fimm16.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_fimm16:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_fimm32.rst b/llvm/docs/AMDGPU/gfx10_fimm32.rst
new file mode 100644
index 0000000..7ff84cc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_fimm32.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_fimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst
new file mode 100644
index 0000000..64d441b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst
@@ -0,0 +1,69 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_hwreg:
+
+hwreg
+===========================
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+ ============ ===================================
+ Bits Description
+ ============ ===================================
+ 5:0 Register *id*.
+ 10:6 First bit *offset* (0..31).
+ 15:11 *Size* in bits (1..32).
+ ============ ===================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
+
+ ==================================== ============================================================================
+ Syntax Description
+ ==================================== ============================================================================
+ hwreg({0..63}) All bits of a register indicated by its *id*.
+ hwreg(<*name*>) All bits of a register indicated by its *name*.
+ hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
+ hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
+ ==================================== ============================================================================
+
+Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Defined register *names* include:
+
+ =================== ==========================================
+ Name Description
+ =================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID Id of wave, simd, compute unit, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ HW_REG_TBA_LO tba_lo register.
+ HW_REG_TBA_HI tba_hi register.
+ HW_REG_TMA_LO tma_lo register.
+ HW_REG_TMA_HI tma_hi register.
+ HW_REG_FLAT_SCR_LO flat_scratch_lo register.
+ HW_REG_FLAT_SCR_HI flat_scratch_hi register.
+ HW_REG_XNACK_MASK xnack_mask register.
+ HW_REG_POPS_PACKER pops_packer register.
+ =================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+ s_getreg_b32 s2, 0x6
+ s_getreg_b32 s2, hwreg(15)
+ s_getreg_b32 s2, hwreg(51, 1, 31)
+ s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
+
diff --git a/llvm/docs/AMDGPU/gfx10_label.rst b/llvm/docs/AMDGPU/gfx10_label.rst
new file mode 100644
index 0000000..288c6c0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_label.rst
@@ -0,0 +1,30 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_label:
+
+label
+===========================
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
+* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. parsed-literal::
+
+ offset = 30
+ s_branch loop_end
+ s_branch 2 + offset
+ s_branch 32
+ loop_end:
+
diff --git a/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
new file mode 100644
index 0000000..bbf04e7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_mad_type_dev:
+
+fx
+===========================
+
+This is an *f32* or *f16* operand depending on instruction modifiers:
+
+* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
new file mode 100644
index 0000000..dfa8c07
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_mod_dpp_sdwa_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
new file mode 100644
index 0000000..b7e0e3e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_mod_sdwa_sext:
+
+m
+===========================
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
new file mode 100644
index 0000000..9f6b6ab
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_mod_vop3_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_msg.rst b/llvm/docs/AMDGPU/gfx10_msg.rst
new file mode 100644
index 0000000..d56daa5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_msg.rst
@@ -0,0 +1,73 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_msg:
+
+msg
+===========================
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+ ============ ======================================================
+ Bits Description
+ ============ ======================================================
+ 3:0 Message *type*.
+ 6:4 Optional *operation*.
+ 9:7 Optional *parameters*.
+ 15:10 Unused.
+ ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:
+
+ ======================================== ========================================================================
+ Syntax Description
+ ======================================== ========================================================================
+ sendmsg(<*type*>) A message identified by its *type*.
+ sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*.
+ sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*.
+ ======================================== ========================================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Each message type supports specific operations:
+
+ ================= ========== ============================== ============ ==========
+ Message name Message Id Supported Operations Operation Id Stream Id
+ ================= ========== ============================== ============ ==========
+ MSG_INTERRUPT 1 \- \- \-
+ MSG_GS 2 GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_DONE 3 GS_OP_NOP 0 \-
+ \ GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_ALLOC_REQ 9 \- \- \-
+ MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
+ \ SYSMSG_OP_REG_RD 2 \-
+ \ SYSMSG_OP_HOST_TRAP_ACK 3 \-
+ \ SYSMSG_OP_TTRACE_PC 4 \-
+ ================= ========== ============================== ============ ==========
+
+Examples:
+
+.. parsed-literal::
+
+ s_sendmsg 0x12
+ s_sendmsg sendmsg(MSG_INTERRUPT)
+ s_sendmsg sendmsg(2, GS_OP_CUT)
+ s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+ s_sendmsg sendmsg(MSG_GS, 2)
+ s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+ s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+
diff --git a/llvm/docs/AMDGPU/gfx10_offset_buf.rst b/llvm/docs/AMDGPU/gfx10_offset_buf.rst
new file mode 100644
index 0000000..99598fd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_offset_buf.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_offset_buf:
+
+soffset
+===========================
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
new file mode 100644
index 0000000..b382317
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_offset_smem_buf:
+
+soffset
+===========================
+
+An unsigned byte offset added to the base address to get memory address.
+
+.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`uimm21<amdgpu_synid_uimm21>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm21<amdgpu_synid_uimm21>`
diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst b/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
new file mode 100644
index 0000000..09ef022
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_offset_smem_plain:
+
+soffset
+===========================
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx10_opt.rst b/llvm/docs/AMDGPU/gfx10_opt.rst
new file mode 100644
index 0000000..d7dbba3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_opt.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_opt:
+
+opt
+===========================
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
diff --git a/llvm/docs/AMDGPU/gfx10_param.rst b/llvm/docs/AMDGPU/gfx10_param.rst
new file mode 100644
index 0000000..afa91e34
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_param.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_param:
+
+param
+===========================
+
+Interpolation parameter to read:
+
+ ============ ===================================
+ Syntax Description
+ ============ ===================================
+ p0 Parameter *P0*.
+ p10 Parameter *P10*.
+ p20 Parameter *P20*.
+ ============ ===================================
+
diff --git a/llvm/docs/AMDGPU/gfx10_perm_smem.rst b/llvm/docs/AMDGPU/gfx10_perm_smem.rst
new file mode 100644
index 0000000..879b33d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_perm_smem.rst
@@ -0,0 +1,24 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_perm_smem:
+
+imm3
+===========================
+
+A bit mask which indicates request permissions.
+
+This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant.
+
+ ============ ==============================
+ Bit Number Description
+ ============ ==============================
+ 0 Request *read* permission.
+ 1 Request *write* permission.
+ 2 Request *execute* permission.
+ ============ ==============================
+
diff --git a/llvm/docs/AMDGPU/gfx10_ret.rst b/llvm/docs/AMDGPU/gfx10_ret.rst
new file mode 100644
index 0000000..2003437
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ret.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ret:
+
+dst
+===========================
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
+
diff --git a/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst
new file mode 100644
index 0000000..a3f454b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_rsrc_buf:
+
+srsrc
+===========================
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst b/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst
new file mode 100644
index 0000000..af830b0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_rsrc_mimg:
+
+srsrc
+===========================
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst
new file mode 100644
index 0000000..2362d0c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_saddr_flat_global:
+
+saddr
+===========================
+
+An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+See :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` for description of available addressing modes.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst
new file mode 100644
index 0000000..8fea5d3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_saddr_flat_scratch:
+
+saddr
+===========================
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_samp_mimg.rst b/llvm/docs/AMDGPU/gfx10_samp_mimg.rst
new file mode 100644
index 0000000..5f2aed0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_samp_mimg.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_samp_mimg:
+
+ssamp
+===========================
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdata128_0.rst b/llvm/docs/AMDGPU/gfx10_sdata128_0.rst
new file mode 100644
index 0000000..19d6e5b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdata128_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdata128_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdata32_0.rst b/llvm/docs/AMDGPU/gfx10_sdata32_0.rst
new file mode 100644
index 0000000..10e10ca
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdata32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdata32_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdata64_0.rst b/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
new file mode 100644
index 0000000..a47fb08
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdata64_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst128_0.rst b/llvm/docs/AMDGPU/gfx10_sdst128_0.rst
new file mode 100644
index 0000000..e1bfc69
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst128_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst128_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst256_0.rst b/llvm/docs/AMDGPU/gfx10_sdst256_0.rst
new file mode 100644
index 0000000..c352bff
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst256_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst256_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_0.rst b/llvm/docs/AMDGPU/gfx10_sdst32_0.rst
new file mode 100644
index 0000000..1000d83
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst32_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_1.rst b/llvm/docs/AMDGPU/gfx10_sdst32_1.rst
new file mode 100644
index 0000000..ddfb348
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst32_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_2.rst b/llvm/docs/AMDGPU/gfx10_sdst32_2.rst
new file mode 100644
index 0000000..41a078b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst32_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst32_2:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst512_0.rst b/llvm/docs/AMDGPU/gfx10_sdst512_0.rst
new file mode 100644
index 0000000..f72a2d5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst512_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst512_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_0.rst b/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
new file mode 100644
index 0000000..a70da80
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst64_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_1.rst b/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
new file mode 100644
index 0000000..483a4e3f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_sdst64_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_simm16.rst b/llvm/docs/AMDGPU/gfx10_simm16.rst
new file mode 100644
index 0000000..eb1d171
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_simm16.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_simm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_src32_0.rst b/llvm/docs/AMDGPU/gfx10_src32_0.rst
new file mode 100644
index 0000000..f4ae944
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_src32_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_1.rst b/llvm/docs/AMDGPU/gfx10_src32_1.rst
new file mode 100644
index 0000000..a1be1e1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_src32_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_2.rst b/llvm/docs/AMDGPU/gfx10_src32_2.rst
new file mode 100644
index 0000000..9b8fd6f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_3.rst b/llvm/docs/AMDGPU/gfx10_src32_3.rst
new file mode 100644
index 0000000..b934822
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_src64_0.rst b/llvm/docs/AMDGPU/gfx10_src64_0.rst
new file mode 100644
index 0000000..f88ccf2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_src64_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src_exp.rst b/llvm/docs/AMDGPU/gfx10_src_exp.rst
new file mode 100644
index 0000000..4dd387a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src_exp.rst
@@ -0,0 +1,28 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_src_exp:
+
+vsrc
+===========================
+
+Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+
+* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
+* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
+
+An example:
+
+.. parsed-literal::
+
+ exp mrtz v3, v3, off, off compr
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst
new file mode 100644
index 0000000..e444898
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc32_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst
new file mode 100644
index 0000000..4fdbe1c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc32_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst
new file mode 100644
index 0000000..1b46e77
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc32_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst
new file mode 100644
index 0000000..ec6b115
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc32_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst
new file mode 100644
index 0000000..bba8d5a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc32_4:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst
new file mode 100644
index 0000000..a0b1bbf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc32_5:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
new file mode 100644
index 0000000..77468262
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc64_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
new file mode 100644
index 0000000..bd13d35
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_ssrc64_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_tgt.rst b/llvm/docs/AMDGPU/gfx10_tgt.rst
new file mode 100644
index 0000000..b6569c7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_tgt.rst
@@ -0,0 +1,25 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_tgt:
+
+tgt
+===========================
+
+An export target:
+
+ ============== ===================================
+ Syntax Description
+ ============== ===================================
+ pos{0..4} Copy vertex position 0..4.
+ param{0..31} Copy vertex parameter 0..31.
+ mrt{0..7} Copy pixel color to the MRTs 0..7.
+ mrtz Copy pixel depth (Z) data.
+ prim Copy primitive (connectivity) data.
+ null Copy nothing.
+ ============== ===================================
+
diff --git a/llvm/docs/AMDGPU/gfx10_type_dev.rst b/llvm/docs/AMDGPU/gfx10_type_dev.rst
new file mode 100644
index 0000000..8978fbe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_type_dev.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_type_dev:
+
+Type deviation
+===========================
+
+*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
+
diff --git a/llvm/docs/AMDGPU/gfx10_uimm16.rst b/llvm/docs/AMDGPU/gfx10_uimm16.rst
new file mode 100644
index 0000000..f4bfe8c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_uimm16.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_uimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
new file mode 100644
index 0000000..0d44a1a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vaddr_flat_global:
+
+vaddr
+===========================
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid10_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid10_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid10_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
+
+.. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst
new file mode 100644
index 0000000..cc6d1af
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vaddr_flat_scratch:
+
+vaddr
+===========================
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_vcc_32.rst b/llvm/docs/AMDGPU/gfx10_vcc_32.rst
new file mode 100644
index 0000000..1e73007
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vcc_32.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vcc_32:
+
+vcc
+===========================
+
+Vector condition code. This operand depends on wavefront size:
+
+* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
+* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.
+
diff --git a/llvm/docs/AMDGPU/gfx10_vdata128_0.rst b/llvm/docs/AMDGPU/gfx10_vdata128_0.rst
new file mode 100644
index 0000000..0e25049
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata128_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdata128_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata32_0.rst b/llvm/docs/AMDGPU/gfx10_vdata32_0.rst
new file mode 100644
index 0000000..e2ddcee
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdata32_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata64_0.rst b/llvm/docs/AMDGPU/gfx10_vdata64_0.rst
new file mode 100644
index 0000000..4552a39
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdata64_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata96_0.rst b/llvm/docs/AMDGPU/gfx10_vdata96_0.rst
new file mode 100644
index 0000000..084825a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata96_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdata96_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst128_0.rst b/llvm/docs/AMDGPU/gfx10_vdst128_0.rst
new file mode 100644
index 0000000..a0a786c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst128_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdst128_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst32_0.rst b/llvm/docs/AMDGPU/gfx10_vdst32_0.rst
new file mode 100644
index 0000000..d04548e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdst32_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst64_0.rst b/llvm/docs/AMDGPU/gfx10_vdst64_0.rst
new file mode 100644
index 0000000..6e44c28
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdst64_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst96_0.rst b/llvm/docs/AMDGPU/gfx10_vdst96_0.rst
new file mode 100644
index 0000000..a30e2ee
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst96_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vdst96_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst
new file mode 100644
index 0000000..1808061
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vsrc128_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst
new file mode 100644
index 0000000..95cecb4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vsrc32_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst
new file mode 100644
index 0000000..fd8c6bd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst
new file mode 100644
index 0000000..56c8fff
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_vsrc64_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
new file mode 100644
index 0000000..e4c4bcd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
@@ -0,0 +1,56 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_waitcnt:
+
+waitcnt
+===========================
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+ ============ ======================================================
+ Bits Description
+ ============ ======================================================
+ 3:0 VM_CNT: vector memory operations count, lower bits.
+ 6:4 EXP_CNT: export count.
+ 11:8 LGKM_CNT: LDS, GDS, Constant and Message count.
+ 15:14 VM_CNT: vector memory operations count, upper bits.
+ ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
+or as a combination of the following symbolic helpers:
+
+ ====================== ======================================================================
+ Syntax Description
+ ====================== ======================================================================
+ vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value.
+ expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+ lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+ vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value).
+ expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+ lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+ ====================== ======================================================================
+
+These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ s_waitcnt 0
+ s_waitcnt vmcnt(1)
+ s_waitcnt expcnt(2) lgkmcnt(3)
+ s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
+ s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+ s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
+
diff --git a/llvm/docs/AMDGPU/gfx10_wsdst.rst b/llvm/docs/AMDGPU/gfx10_wsdst.rst
new file mode 100644
index 0000000..1e39990
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_wsdst.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_wsdst:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_wssrc.rst b/llvm/docs/AMDGPU/gfx10_wssrc.rst
new file mode 100644
index 0000000..35fdb02
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_wssrc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid10_wssrc:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx7_offset_buf.rst b/llvm/docs/AMDGPU/gfx7_offset_buf.rst
index c36df06..b78affa 100644
--- a/llvm/docs/AMDGPU/gfx7_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx7_offset_buf.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_0.rst b/llvm/docs/AMDGPU/gfx7_src32_0.rst
index 22ff73d..6a9c977 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_0.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_1.rst b/llvm/docs/AMDGPU/gfx7_src32_1.rst
index 0059459..990d229 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_1.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_2.rst b/llvm/docs/AMDGPU/gfx7_src32_2.rst
index b939c45..2fdb646 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_2.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_3.rst b/llvm/docs/AMDGPU/gfx7_src32_3.rst
index 83aa9ca..19bbde9 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_3.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_3.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_4.rst b/llvm/docs/AMDGPU/gfx7_src32_4.rst
new file mode 100644
index 0000000..7b0c3a8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_src32_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_5.rst b/llvm/docs/AMDGPU/gfx7_src32_5.rst
new file mode 100644
index 0000000..bcfbaeb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_src32_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_src32_5:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_6.rst b/llvm/docs/AMDGPU/gfx7_src32_6.rst
new file mode 100644
index 0000000..8c49d59
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_src32_6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_src32_6:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_src64_0.rst b/llvm/docs/AMDGPU/gfx7_src64_0.rst
index a19b6ee..9088418 100644
--- a/llvm/docs/AMDGPU/gfx7_src64_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_src64_0.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_src64_1.rst b/llvm/docs/AMDGPU/gfx7_src64_1.rst
index c81864c..feb657c 100644
--- a/llvm/docs/AMDGPU/gfx7_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx7_src64_1.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src64_2.rst b/llvm/docs/AMDGPU/gfx7_src64_2.rst
index 189245e..4a50df7 100644
--- a/llvm/docs/AMDGPU/gfx7_src64_2.rst
+++ b/llvm/docs/AMDGPU/gfx7_src64_2.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst
index 843db24..589d9cc 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst
index 6e626d8..4f04b0b 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst
index 68a2415..2ec4af2 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst
index 669ae4e..e07ffe5 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst
new file mode 100644
index 0000000..71402a7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_ssrc32_5:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst
new file mode 100644
index 0000000..32bc305
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_ssrc32_6:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst
index 283e7ea..49add61 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst
index 344147f..5255930 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst
new file mode 100644
index 0000000..063216a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx8_offset_buf.rst b/llvm/docs/AMDGPU/gfx8_offset_buf.rst
index 42c4524..7b72bb6 100644
--- a/llvm/docs/AMDGPU/gfx8_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx8_offset_buf.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_0.rst b/llvm/docs/AMDGPU/gfx8_src32_0.rst
index a9c11fe..2e4d42b 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_0.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_1.rst b/llvm/docs/AMDGPU/gfx8_src32_1.rst
index 67dcdc8..ea64ab1 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_1.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_2.rst b/llvm/docs/AMDGPU/gfx8_src32_2.rst
new file mode 100644
index 0000000..016e7b9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid8_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_3.rst b/llvm/docs/AMDGPU/gfx8_src32_3.rst
new file mode 100644
index 0000000..ea3164d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid8_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src64_0.rst b/llvm/docs/AMDGPU/gfx8_src64_0.rst
index 573fd68..d62c37e 100644
--- a/llvm/docs/AMDGPU/gfx8_src64_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_src64_0.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src64_1.rst b/llvm/docs/AMDGPU/gfx8_src64_1.rst
index d2c78b7..cd5ab8b 100644
--- a/llvm/docs/AMDGPU/gfx8_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx8_src64_1.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst
index 82d18b1..1f7d9fb 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst
index 02d90a4..eb5e224 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst
index b8389dc..6c7efe5 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst
index 209dffc..3252202 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst
new file mode 100644
index 0000000..5ed15a1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid8_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx9_msg.rst b/llvm/docs/AMDGPU/gfx9_msg.rst
index f18cff46..8988485 100644
--- a/llvm/docs/AMDGPU/gfx9_msg.rst
+++ b/llvm/docs/AMDGPU/gfx9_msg.rst
@@ -52,6 +52,7 @@
\ GS_OP_CUT 1 Optional
\ GS_OP_EMIT 2 Optional
\ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_ALLOC_REQ 9 \- \- \-
MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
\ SYSMSG_OP_REG_RD 2 \-
\ SYSMSG_OP_HOST_TRAP_ACK 3 \-
diff --git a/llvm/docs/AMDGPU/gfx9_offset_buf.rst b/llvm/docs/AMDGPU/gfx9_offset_buf.rst
index ec6cc33..7a01fde 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_offset_buf.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_0.rst b/llvm/docs/AMDGPU/gfx9_src32_0.rst
index 288ccbb..d4c4958 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_0.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_1.rst b/llvm/docs/AMDGPU/gfx9_src32_1.rst
index a06764d..b96594c 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_1.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_2.rst b/llvm/docs/AMDGPU/gfx9_src32_2.rst
new file mode 100644
index 0000000..045b913
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid9_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_3.rst b/llvm/docs/AMDGPU/gfx9_src32_3.rst
new file mode 100644
index 0000000..2bb7972
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid9_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src64_0.rst b/llvm/docs/AMDGPU/gfx9_src64_0.rst
index f8ef842..cc6e5ca 100644
--- a/llvm/docs/AMDGPU/gfx9_src64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_src64_0.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src64_1.rst b/llvm/docs/AMDGPU/gfx9_src64_1.rst
index fe7b7fd..9075c24 100644
--- a/llvm/docs/AMDGPU/gfx9_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src64_1.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
index 25d6b37..d52f688 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
index 7e55427..b151fbb 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
@@ -14,4 +14,4 @@
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
index b2f86e1..4a3ef06 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
index 72d2c46..a9aa6dc 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
@@ -14,4 +14,4 @@
*Size:* 2 dwords.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
new file mode 100644
index 0000000..5a5b921
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid9_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`