AMDGPU: Disambiguate v3f16 format in load/store tables
Currently the searchable tables report the number of dwords. These
round to the same number for 3 and 4 component d16
instructions. Change this to report the number of elements so this
isn't ambiguous.
llvm-svn: 369202
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 30ee082..70fb377 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -402,7 +402,8 @@
const unsigned Opc = MI.getOpcode();
if (TII->isMUBUF(MI)) {
- return AMDGPU::getMUBUFDwords(Opc);
+ // FIXME: Handle d16 correctly
+ return AMDGPU::getMUBUFElements(Opc);
}
switch (Opc) {
@@ -977,6 +978,7 @@
switch (CI.InstClass) {
default:
+ // FIXME: Handle d16 correctly
return AMDGPU::getMUBUFOpcode(CI.InstClass, Width);
case UNKNOWN:
llvm_unreachable("Unknown instruction class");