AMDGPU: Disambiguate v3f16 format in load/store tables
Currently the searchable tables report the number of dwords. These
round to the same number for 3 and 4 component d16
instructions. Change this to report the number of elements so this
isn't ambiguous.
llvm-svn: 369202
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index ef50d37..22a6426 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -131,7 +131,7 @@
struct MUBUFInfo {
uint16_t Opcode;
uint16_t BaseOpcode;
- uint8_t dwords;
+ uint8_t elements;
bool has_vaddr;
bool has_srsrc;
bool has_soffset;
@@ -146,14 +146,14 @@
return Info ? Info->BaseOpcode : -1;
}
-int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords) {
- const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndDwords(BaseOpc, Dwords);
+int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) {
+ const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
return Info ? Info->Opcode : -1;
}
-int getMUBUFDwords(unsigned Opc) {
+int getMUBUFElements(unsigned Opc) {
const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
- return Info ? Info->dwords : 0;
+ return Info ? Info->elements : 0;
}
bool getMUBUFHasVAddr(unsigned Opc) {