ee7c7ecd0366214d6f7a6d38fb4d8c16d98cbb85 - toolchain/llvm-project

commit	ee7c7ecd0366214d6f7a6d38fb4d8c16d98cbb85	[log] [tgz]
author	Alex Bradbury <asb@lowrisc.org>	Thu Oct 19 14:29:03 2017 +0000
committer	Alex Bradbury <asb@lowrisc.org>	Thu Oct 19 14:29:03 2017 +0000
tree	200f2b22394cc9ed5d25bb19ea349287de54faff
parent	27c1f464e6aa287bfcfe775df10b5c92504a4534 [diff]

[RISCV] Prepare for the use of variable-sized register classes

While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.

llvm-svn: 316159

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp[diff]
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h[diff]
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp[diff]
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp[diff]
llvm/lib/Target/RISCV/RISCV.td[diff]
llvm/lib/Target/RISCV/RISCVInstrFormats.td[diff]
llvm/lib/Target/RISCV/RISCVInstrInfo.td[diff]
llvm/lib/Target/RISCV/RISCVRegisterInfo.td[diff]

8 files changed

tree: 200f2b22394cc9ed5d25bb19ea349287de54faff

clang/
clang-tools-extra/
compiler-rt/
debuginfo-tests/
libclc/
libcxx/
libcxxabi/
libunwind/
lld/
lldb/
llgo/
llvm/
openmp/
parallel-libs/
polly/