commit d1815dacb00d2f5845449a20f6e749119962aa87
author Petar Avramovic <Petar.Avramovic@rt-rk.com> Wed Oct 23 11:22:07 2019 +0200
committer Petar Avramovic <Petar.Avramovic@rt-rk.com> Wed Oct 23 11:22:07 2019 +0200
tree 8d6d97796519538157a99cfcef57c24aaabf3650
parent c46d24f5c3141e9a9f2bdd9d5c38b98feffc8760

[MIPS GlobalISel] Select MSA vector generic and builtin mul

Select vector G_MUL for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
Manual selection of G_MUL is now done for gprb only.
__builtin_msa_mulv_<format> will be transformed into G_MUL
in legalizeIntrinsic and selected in the same way.

Differential Revision: https://reviews.llvm.org/D69310

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index f8fc7cb..9952b5c 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -239,7 +239,9 @@
     return true;
   }
 
-  if (I.getOpcode() == Mips::G_MUL) {
+  if (I.getOpcode() == Mips::G_MUL &&
+      (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
+       Mips::GPRBRegBankID)) {
     MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
                             .add(I.getOperand(0))
                             .add(I.getOperand(1))

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index ce203b3..3c931d7 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -61,11 +61,7 @@
   const LLT v2s64 = LLT::vector(2, 64);
   const LLT p0 = LLT::pointer(0, 32);
 
-  getActionDefinitionsBuilder(G_MUL)
-      .legalFor({s32})
-      .clampScalar(0, s32, s32);
-
-  getActionDefinitionsBuilder({G_ADD, G_SUB})
+  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
       .legalIf([=, &ST](const LegalityQuery &Query) {
         if (CheckTyN(0, Query, {s32}))
           return true;
@@ -377,6 +373,11 @@
     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
   case Intrinsic::mips_subvi_d:
     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
+  case Intrinsic::mips_mulv_b:
+  case Intrinsic::mips_mulv_h:
+  case Intrinsic::mips_mulv_w:
+  case Intrinsic::mips_mulv_d:
+    return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
   default:
     break;
   }

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 51a1cf3..f8531f8 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -437,7 +437,6 @@
 
   switch (Opc) {
   case G_TRUNC:
-  case G_MUL:
   case G_UMULH:
   case G_ZEXTLOAD:
   case G_SEXTLOAD:
@@ -460,6 +459,7 @@
     break;
   case G_ADD:
   case G_SUB:
+  case G_MUL:
     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
     if (Op0Size == 128)
       OperandsMapping = getMSAMapping(MF);