commit d1de276c1697777c8a3f906ddfc9b43f09956d0a
author Dale Johannesen <dalej@apple.com> Mon May 21 22:42:04 2007 +0000
committer Dale Johannesen <dalej@apple.com> Mon May 21 22:42:04 2007 +0000
tree 129cee80faa6d8a681272908a44e9767920d9d9f
parent e26c0916a3fda9188cf118f1e0951d18574614a9

Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores.  Cosmetic.

llvm-svn: 37271

llvm/lib/Target/ARM/ARMInstrInfo.td

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 233c3ae..b187771 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -508,6 +508,8 @@
   : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AXI2<dag ops, string asm, list<dag> pattern>
   : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AXI3<dag ops, string asm, list<dag> pattern>
+  : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AXI4<dag ops, string asm, list<dag> pattern>
   : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
 
@@ -560,7 +562,7 @@
                   "${addr:label}:\n\tldr$p $dst, $addr",
                   [(set GPR:$dst, (load addrmodepc:$addr))]>;
 
-def PICLDZH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
                   "${addr:label}:\n\tldr${p}h $dst, $addr",
                   [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
 
@@ -568,7 +570,7 @@
                   "${addr:label}:\n\tldr${p}b $dst, $addr",
                   [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
 
-def PICLDH  : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDH  : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
                   "${addr:label}:\n\tldr${p}h $dst, $addr",
                   [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
 
@@ -576,11 +578,11 @@
                   "${addr:label}:\n\tldr${p}b $dst, $addr",
                   [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
 
-def PICLDSH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
                   "${addr:label}:\n\tldr${p}sh $dst, $addr",
                   [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
 
-def PICLDSB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
                   "${addr:label}:\n\tldr${p}sb $dst, $addr",
                   [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
 }
@@ -589,7 +591,7 @@
                "${addr:label}:\n\tstr$p $src, $addr",
                [(store GPR:$src, addrmodepc:$addr)]>;
 
-def PICSTRH : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p),
                "${addr:label}:\n\tstr${p}h $src, $addr",
                [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;