diff --git a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
index da6c9ca..be2cdfa 100644
--- a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
+++ b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
@@ -11,7 +11,8 @@
 
 #include "SparcInternals.h"
 #include "SparcRegClassInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/InstrSelectionSupport.h"
@@ -19,48 +20,38 @@
 #include "llvm/Function.h"
 
 namespace {
-  class InsertPrologEpilogCode : public FunctionPass {
-    TargetMachine &Target;
-  public:
-    InsertPrologEpilogCode(TargetMachine &T) : Target(T) {}
-    
+  struct InsertPrologEpilogCode : public MachineFunctionPass {
     const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; }
     
-    bool runOnFunction(Function &F) {
-      MachineFunction &mcodeInfo = MachineFunction::get(&F);
-      if (!mcodeInfo.isCompiledAsLeafMethod()) {
+    bool runOnMachineFunction(MachineFunction &F) {
+      if (!F.getInfo()->isCompiledAsLeafMethod()) {
         InsertPrologCode(F);
         InsertEpilogCode(F);
       }
       return false;
     }
     
-    void InsertPrologCode(Function &F);
-    void InsertEpilogCode(Function &F);
+    void InsertPrologCode(MachineFunction &F);
+    void InsertEpilogCode(MachineFunction &F);
   };
 
 }  // End anonymous namespace
 
 //------------------------------------------------------------------------ 
-// External Function: GetInstructionsForProlog
-// External Function: GetInstructionsForEpilog
-//
-// Purpose:
 //   Create prolog and epilog code for procedure entry and exit
 //------------------------------------------------------------------------ 
 
-void InsertPrologEpilogCode::InsertPrologCode(Function &F)
+void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
 {
   std::vector<MachineInstr*> mvec;
-  MachineInstr* M;
-  const MachineFrameInfo& frameInfo = Target.getFrameInfo();
+  const TargetMachine &TM = MF.getTarget();
+  const TargetFrameInfo& frameInfo = TM.getFrameInfo();
   
   // The second operand is the stack size. If it does not fit in the
   // immediate field, we have to use a free register to hold the size.
   // See the comments below for the choice of this register.
   // 
-  MachineFunction& mcInfo = MachineFunction::get(&F);
-  unsigned staticStackSize = mcInfo.getStaticStackSize();
+  unsigned staticStackSize = MF.getInfo()->getStaticStackSize();
   
   if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
     staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
@@ -70,50 +61,50 @@
     staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
   
   int32_t C = - (int) staticStackSize;
-  int SP = Target.getRegInfo().getStackPointer();
-  if (Target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) {
-    M = BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP);
-    mvec.push_back(M);
+  int SP = TM.getRegInfo().getStackPointer();
+  if (TM.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) {
+    mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP));
   } else {
-      // We have to put the stack size value into a register before SAVE.
-      // Use register %g1 since it is volatile across calls.  Note that the
-      // local (%l) and in (%i) registers cannot be used before the SAVE!
-      // Do this by creating a code sequence equivalent to:
-      //        SETSW -(stackSize), %g1
-      int uregNum = Target.getRegInfo().getUnifiedRegNum(
-                           Target.getRegInfo().getRegClassIDOfType(Type::IntTy),
-                           SparcIntRegClass::g1);
-      
-      M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum);
-      M->setOperandHi32(0);
-      mvec.push_back(M);
-      
-      M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum);
-      M->setOperandLo32(1);
-      mvec.push_back(M);
-      
-      M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum);
-      mvec.push_back(M);
-      
-      // Now generate the SAVE using the value in register %g1
-      M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP);
-      mvec.push_back(M);
-    }
+    // We have to put the stack size value into a register before SAVE.
+    // Use register %g1 since it is volatile across calls.  Note that the
+    // local (%l) and in (%i) registers cannot be used before the SAVE!
+    // Do this by creating a code sequence equivalent to:
+    //        SETSW -(stackSize), %g1
+    int uregNum = TM.getRegInfo().getUnifiedRegNum(
+			 TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
+			 SparcIntRegClass::g1);
 
-  MachineBasicBlock& bbMvec = mcInfo.front();
-  bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
+    MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum);
+    M->setOperandHi32(0);
+    mvec.push_back(M);
+    
+    M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum);
+    M->setOperandLo32(1);
+    mvec.push_back(M);
+    
+    M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum);
+    mvec.push_back(M);
+    
+    // Now generate the SAVE using the value in register %g1
+    M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP);
+    mvec.push_back(M);
+  }
+
+  MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end());
 }
 
-void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
+void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
 {
-  MachineFunction &MF = MachineFunction::get(&F);
+  const TargetMachine &TM = MF.getTarget();
+  const MachineInstrInfo &MII = TM.getInstrInfo();
+
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
     MachineBasicBlock &MBB = *I;
     BasicBlock &BB = *I->getBasicBlock();
     Instruction *TermInst = (Instruction*)BB.getTerminator();
     if (TermInst->getOpcode() == Instruction::Ret)
       {
-        int ZR = Target.getRegInfo().getZeroRegNum();
+        int ZR = TM.getRegInfo().getZeroRegNum();
         MachineInstr *Restore =
           BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR);
         
@@ -121,7 +112,6 @@
           MachineCodeForInstruction::get(TermInst);
         
         // Remove the NOPs in the delay slots of the return instruction
-        const MachineInstrInfo &mii = Target.getInstrInfo();
         unsigned numNOPs = 0;
         while (termMvec.back()->getOpCode() == NOP)
           {
@@ -134,7 +124,7 @@
         
         // Check that we found the right number of NOPs and have the right
         // number of instructions to replace them.
-        unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode());
+        unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode());
         assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
         assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
         
@@ -145,5 +135,5 @@
 }
 
 Pass* UltraSparc::getPrologEpilogInsertionPass() {
-  return new InsertPrologEpilogCode(*this);
+  return new InsertPrologEpilogCode();
 }