[PowerPC] Don't assume ADDISdtprelHA's source is r3
Even through ADDISdtprelHA generally has r3 as its source register, it is
possible for the instruction scheduler to move things around such that some
other register is the source. We need to print the actual source register, not
always r3. Fixes PR24394.
The test case will come in a follow-up commit because it depends on MIR
target-flags parsing.
llvm-svn: 246372
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 2ce7501..a779338 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -947,11 +947,11 @@
return;
}
case PPC::ADDISdtprelHA:
- // Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
- // Into: %Xd = ADDIS8 %X3, sym@dtprel@ha
+ // Transform: %Xd = ADDISdtprelHA %Xs, <ga:@sym>
+ // Into: %Xd = ADDIS8 %Xs, sym@dtprel@ha
case PPC::ADDISdtprelHA32: {
- // Transform: %Rd = ADDISdtprelHA32 %R3, <ga:@sym>
- // Into: %Rd = ADDIS %R3, sym@dtprel@ha
+ // Transform: %Rd = ADDISdtprelHA32 %Rs, <ga:@sym>
+ // Into: %Rd = ADDIS %Rs, sym@dtprel@ha
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -962,7 +962,7 @@
*OutStreamer,
MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
.addReg(MI->getOperand(0).getReg())
- .addReg(Subtarget->isPPC64() ? PPC::X3 : PPC::R3)
+ .addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
return;
}