commit d3260128af60e9d0df90610550dfa5985a6f2e0e
author Duraid Madina <duraid@octopus.com.au> Fri Nov 04 10:01:10 2005 +0000
committer Duraid Madina <duraid@octopus.com.au> Fri Nov 04 10:01:10 2005 +0000
tree 675fa6aac7f8ab175f49be14b4205f6e658a51a6
parent fc1d1b249921fba272d8c31392419db1ac481f27

kill redundant SP/GP/RP save/restores across calls

llvm-svn: 24183

llvm/lib/Target/IA64/IA64ISelLowering.cpp

diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
index 37f15ee..d757496 100644
--- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
@@ -192,20 +192,21 @@
   VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
   BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
   // we create a PSEUDO_ALLOC (pseudo)instruction for now
-
+/*
   BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
 
   // hmm:
   BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
   BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
   // ..hmm.
-
+  
   BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
 
   // hmm:
   BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
   BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
   // ..hmm.
+*/
 
   unsigned tempOffset=0;