commit d37dc77b6e52d46f2388070f2fd530424b49a8cd
author Geoff Berry <gberry@codeaurora.org> Mon Jan 29 18:47:48 2018 +0000
committer Geoff Berry <gberry@codeaurora.org> Mon Jan 29 18:47:48 2018 +0000
tree fe09801732f33a3e4f05668d1eba70de4f02a05a
parent d5f76ad37fb235c684d551251eb8c0e204bde134

[AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs

Summary:
Fix a few places that were modifying code after register
allocation to set the renamable bit correctly to avoid failing the
validation added in D42449.

llvm-svn: 323675

llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index 2dc6f27..e77c98a 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -246,6 +246,7 @@
         DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
 
         PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC);
+        PrepareExecInst->getOperand(0).setIsRenamable(false);
 
         DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
 
@@ -352,7 +353,8 @@
 
     for (MachineInstr *OtherInst : OtherUseInsts) {
       OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC,
-                                    AMDGPU::NoSubRegister, *TRI);
+                                    AMDGPU::NoSubRegister, *TRI,
+                                    /*ClearIsRenamable=*/true);
     }
   }