[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
Differential Revision: https://reviews.llvm.org/D38347
llvm-svn: 316085
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 737450d..a29a2ee 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -5340,8 +5340,14 @@
} else
Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
- Inst.addOperand(MCOperand::createImm(ARMCC::AL));
- Inst.addOperand(MCOperand::createReg(0));
+ if (featureBits[ARM::ModeThumb]) {
+ Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+ Inst.addOperand(MCOperand::createReg(0));
+ } else {
+ unsigned pred = fieldFromInstruction(Val, 28, 4);
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
return S;
}