Introduce codegen for the Signal Processing Engine
Summary:
The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1,
e500v2, and several e200 cores. This adds support targeting the e500v2,
as this is more common than the e500v1, and is in SoCs still on the
market.
This patch is very intrusive because the SPE is binary incompatible with
the traditional FPU. After discussing with others, the cleanest
solution was to make both SPE and FPU features on top of a base PowerPC
subset, so all FPU instructions are now wrapped with HasFPU predicates.
Supported by this are:
* Code generation following the SPE ABI at the LLVM IR level (calling
conventions)
* Single- and Double-precision math at the level supported by the APU.
Still to do:
* Vector operations
* SPE intrinsics
As this changes the Callee-saved register list order, one test, which
tests the precise generated code, was updated to account for the new
register order.
Reviewed by: nemanjai
Differential Revision: https://reviews.llvm.org/D44830
llvm-svn: 337347
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 06152d0..6cec664 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3616,9 +3616,59 @@
Opc = PPC::CMPD;
}
} else if (LHS.getValueType() == MVT::f32) {
- Opc = PPC::FCMPUS;
+ if (PPCSubTarget->hasSPE()) {
+ switch (CC) {
+ default:
+ case ISD::SETEQ:
+ case ISD::SETNE:
+ Opc = PPC::EFSCMPEQ;
+ break;
+ case ISD::SETLT:
+ case ISD::SETGE:
+ case ISD::SETOLT:
+ case ISD::SETOGE:
+ case ISD::SETULT:
+ case ISD::SETUGE:
+ Opc = PPC::EFSCMPLT;
+ break;
+ case ISD::SETGT:
+ case ISD::SETLE:
+ case ISD::SETOGT:
+ case ISD::SETOLE:
+ case ISD::SETUGT:
+ case ISD::SETULE:
+ Opc = PPC::EFSCMPGT;
+ break;
+ }
+ } else
+ Opc = PPC::FCMPUS;
} else if (LHS.getValueType() == MVT::f64) {
- Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
+ if (PPCSubTarget->hasSPE()) {
+ switch (CC) {
+ default:
+ case ISD::SETEQ:
+ case ISD::SETNE:
+ Opc = PPC::EFDCMPEQ;
+ break;
+ case ISD::SETLT:
+ case ISD::SETGE:
+ case ISD::SETOLT:
+ case ISD::SETOGE:
+ case ISD::SETULT:
+ case ISD::SETUGE:
+ Opc = PPC::EFDCMPLT;
+ break;
+ case ISD::SETGT:
+ case ISD::SETLE:
+ case ISD::SETOGT:
+ case ISD::SETOLE:
+ case ISD::SETUGT:
+ case ISD::SETULE:
+ Opc = PPC::EFDCMPGT;
+ break;
+ }
+ } else
+ Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
} else {
assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
@@ -3896,7 +3946,7 @@
// Altivec Vector compare instructions do not set any CR register by default and
// vector compare operations return the same type as the operands.
if (LHS.getValueType().isVector()) {
- if (PPCSubTarget->hasQPX())
+ if (PPCSubTarget->hasQPX() || PPCSubTarget->hasSPE())
return false;
EVT VecVT = LHS.getValueType();
@@ -3926,6 +3976,12 @@
SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
SDValue IntCR;
+ // SPE e*cmp* instructions only set the 'gt' bit, so hard-code that
+ // The correct compare instruction is already set by SelectCC()
+ if (PPCSubTarget->hasSPE() && LHS.getValueType().isFloatingPoint()) {
+ Idx = 1;
+ }
+
// Force the ccreg into CR7.
SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
@@ -4557,18 +4613,24 @@
SelectCCOp = PPC::SELECT_CC_I4;
else if (N->getValueType(0) == MVT::i64)
SelectCCOp = PPC::SELECT_CC_I8;
- else if (N->getValueType(0) == MVT::f32)
+ else if (N->getValueType(0) == MVT::f32) {
if (PPCSubTarget->hasP8Vector())
SelectCCOp = PPC::SELECT_CC_VSSRC;
+ else if (PPCSubTarget->hasSPE())
+ SelectCCOp = PPC::SELECT_CC_SPE4;
else
SelectCCOp = PPC::SELECT_CC_F4;
- else if (N->getValueType(0) == MVT::f64)
+ } else if (N->getValueType(0) == MVT::f64) {
if (PPCSubTarget->hasVSX())
SelectCCOp = PPC::SELECT_CC_VSFRC;
+ else if (PPCSubTarget->hasSPE())
+ SelectCCOp = PPC::SELECT_CC_SPE;
else
SelectCCOp = PPC::SELECT_CC_F8;
- else if (N->getValueType(0) == MVT::f128)
+ } else if (N->getValueType(0) == MVT::f128)
SelectCCOp = PPC::SELECT_CC_F16;
+ else if (PPCSubTarget->hasSPE())
+ SelectCCOp = PPC::SELECT_CC_SPE;
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
SelectCCOp = PPC::SELECT_CC_QFRC;
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
@@ -5352,6 +5414,8 @@
case PPC::SELECT_QFRC:
case PPC::SELECT_QSRC:
case PPC::SELECT_QBRC:
+ case PPC::SELECT_SPE:
+ case PPC::SELECT_SPE4:
case PPC::SELECT_VRRC:
case PPC::SELECT_VSFRC:
case PPC::SELECT_VSSRC:
@@ -5671,6 +5735,8 @@
case PPC::SELECT_QFRC:
case PPC::SELECT_QSRC:
case PPC::SELECT_QBRC:
+ case PPC::SELECT_SPE:
+ case PPC::SELECT_SPE4:
case PPC::SELECT_VRRC:
case PPC::SELECT_VSFRC:
case PPC::SELECT_VSSRC: