ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index b6bfece..f8aee86 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -953,8 +953,8 @@
case ARM::LDR_PRE:
case ARM::LDRBT_POST_REG:
case ARM::LDRBT_POST_IMM:
- case ARM::LDRTr:
- case ARM::LDRTi:
+ case ARM::LDRT_POST_REG:
+ case ARM::LDRT_POST_IMM:
DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
break;
default: