[ARM64] Port over missing subtarget features, and CPU definitions from AArch64.
llvm-svn: 206198
diff --git a/llvm/lib/Target/ARM64/ARM64.td b/llvm/lib/Target/ARM64/ARM64.td
index 3eef8b2..23fe65a 100644
--- a/llvm/lib/Target/ARM64/ARM64.td
+++ b/llvm/lib/Target/ARM64/ARM64.td
@@ -20,6 +20,15 @@
// ARM64 Subtarget features.
//
+def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
+ "Enable ARMv8 FP">;
+
+def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
+ "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
+
+def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
+ "Enable cryptographic instructions">;
+
/// Cyclone has register move instructions which are "free".
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
"Has zereo-cycle register moves">;
@@ -49,9 +58,31 @@
//
include "ARM64SchedCyclone.td"
-def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
+def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
+ "Cortex-A53 ARM processors",
+ [FeatureFPARMv8,
+ FeatureNEON,
+ FeatureCrypto]>;
-def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
+def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
+ "Cortex-A57 ARM processors",
+ [FeatureFPARMv8,
+ FeatureNEON,
+ FeatureCrypto]>;
+
+def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
+ "Cyclone",
+ [FeatureFPARMv8,
+ FeatureNEON,
+ FeatureCrypto,
+ FeatureZCRegMove, FeatureZCZeroing]>;
+
+def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, FeatureNEON]>;
+
+def : ProcessorModel<"cortex-a53", NoSchedModel, [ProcA53]>;
+def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
+
+def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
//===----------------------------------------------------------------------===//
// Assembly parser
diff --git a/llvm/lib/Target/ARM64/ARM64Subtarget.cpp b/llvm/lib/Target/ARM64/ARM64Subtarget.cpp
index 14b5444..30c1264 100644
--- a/llvm/lib/Target/ARM64/ARM64Subtarget.cpp
+++ b/llvm/lib/Target/ARM64/ARM64Subtarget.cpp
@@ -26,12 +26,15 @@
ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
- : ARM64GenSubtargetInfo(TT, CPU, FS), HasZeroCycleRegMove(false),
- HasZeroCycleZeroing(false), CPUString(CPU), TargetTriple(TT) {
+ : ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
+ HasFPARMv8(false), HasNEON(false), HasCrypto(false),
+ HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
+ CPUString(CPU), TargetTriple(TT) {
// Determine default and user-specified characteristics
+ // FIXME: Make this darwin-only.
if (CPUString.empty())
- // We default to Cyclone for now.
+ // We default to Cyclone for now, on Darwin.
CPUString = "cyclone";
ParseSubtargetFeatures(CPUString, FS);
diff --git a/llvm/lib/Target/ARM64/ARM64Subtarget.h b/llvm/lib/Target/ARM64/ARM64Subtarget.h
index 1cbd79e..584c41b 100644
--- a/llvm/lib/Target/ARM64/ARM64Subtarget.h
+++ b/llvm/lib/Target/ARM64/ARM64Subtarget.h
@@ -27,6 +27,15 @@
class ARM64Subtarget : public ARM64GenSubtargetInfo {
protected:
+ enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
+
+ /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
+ ARMProcFamilyEnum ARMProcFamily;
+
+ bool HasFPARMv8;
+ bool HasNEON;
+ bool HasCrypto;
+
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove;
@@ -51,6 +60,10 @@
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
+ bool hasFPARMv8() const { return HasFPARMv8; }
+ bool hasNEON() const { return HasNEON; }
+ bool hasCrypto() const { return HasCrypto; }
+
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }