[llvm-exegesis] Add support for AVX512 explicit rounding operands.
Reviewers: gchatelet
Subscribers: tschuett, mstojanovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73083
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
index 5ad4992..808ea34 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -198,6 +198,24 @@
}
}
+TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
+ // - VCVTUSI642SDZrrb_Int
+ // - Op0 Explicit Def RegClass(VR128X)
+ // - Op1 Explicit Use RegClass(VR128X)
+ // - Op2 Explicit Use STATIC_ROUNDING
+ // - Op2 Explicit Use RegClass(GR64)
+ // - Op4 Implicit Use Reg(MXSCR)
+ const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
+ const Instruction &Instr = State.getIC().getInstr(Opcode);
+ auto Configs =
+ Generator.generateConfigurations(Instr, State.getRATC().emptyRegisters());
+ ASSERT_FALSE(Configs.takeError());
+ ASSERT_THAT(*Configs, SizeIs(1));
+ const BenchmarkCode &BC = (*Configs)[0];
+ ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
+ ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
+}
+
TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) {
// - BNDCL32rr
// - Op0 Explicit Use RegClass(BNDR)