Recommit r310809 with a fix for the spill problem
This patch re-commits the patch that was pulled out due to a
problem it caused, but with a fix for the problem. The fix
was reviewed separately by Eric Christopher and Hal Finkel.
Differential Revision: https://reviews.llvm.org/D38054
llvm-svn: 313978
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
new file mode 100644
index 0000000..ba37281
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
@@ -0,0 +1,68 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}