[GISel]: Attach missing range metadata while translating G_LOADs
https://reviews.llvm.org/D65048
Attach range information to G_LOAD when only defining one register.
reviewed by: arsenm
llvm-svn: 366656
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index f322445..7c90d57 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -879,7 +879,8 @@
return true;
}
-
+ const MDNode *Ranges =
+ Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr;
for (unsigned i = 0; i < Regs.size(); ++i) {
Register Addr;
MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);
@@ -888,7 +889,7 @@
unsigned BaseAlign = getMemOpAlignment(LI);
auto MMO = MF->getMachineMemOperand(
Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
- MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
+ MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), Ranges,
LI.getSyncScopeID(), LI.getOrdering());
MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index d031380..57b8264 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -351,7 +351,9 @@
; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
-; CHECK: $x0 = COPY [[SUM3]]
+; CHECK: [[VAL4:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, !range !0)
+; CHECK: [[SUM4:%[0-9]+]]:_(s64) = G_ADD [[SUM3]], [[VAL4]]
+; CHECK: $x0 = COPY [[SUM4]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
%val1 = load i64, i64* %addr, align 16
@@ -361,7 +363,10 @@
%val3 = load volatile i64, i64* %addr
%sum3 = add i64 %sum2, %val3
- ret i64 %sum3
+
+ %val4 = load i64, i64* %addr, !range !0
+ %sum4 = add i64 %sum3, %val4
+ ret i64 %sum4
}
; CHECK-LABEL: name: store
@@ -2334,3 +2339,5 @@
call void @llvm.var.annotation(i8* %0, i8* %1, i8* %2, i32 %3)
ret void
}
+
+!0 = !{ i64 0, i64 2 }