commit d7bdf24f32b7f7b7fe81ff38b51d94478a6e3e87
author Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> Fri Sep 30 16:50:36 2016 +0000
committer Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> Fri Sep 30 16:50:36 2016 +0000
tree f883a841876d2eb8fdbff02699f15e2b0eecc1cd
parent 51f514d853183f226af7a7c68730e4a0507c171f

[AMDGPU] Ask subtarget if waitcnt instruction is needed before barrier instruction

Differential Revision: https://reviews.llvm.org/D24985

llvm-svn: 282875

llvm/lib/Target/AMDGPU/SIInsertWaits.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
index d24588d..b9551be 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
@@ -590,8 +590,9 @@
       // S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
       // but we also want to wait for any other outstanding transfers before
       // signalling other hardware blocks
-      if (I->getOpcode() == AMDGPU::S_BARRIER ||
-          I->getOpcode() == AMDGPU::S_SENDMSG)
+      if ((I->getOpcode() == AMDGPU::S_BARRIER &&
+               ST->needWaitcntBeforeBarrier()) ||
+           I->getOpcode() == AMDGPU::S_SENDMSG)
         Required = LastIssued;
       else
         Required = handleOperands(*I);