Model cache size and associativity in TargetTransformInfo
Summary:
We add the precise cache sizes and associativity for the following Intel
architectures:
- Penry
- Nehalem
- Westmere
- Sandy Bridge
- Ivy Bridge
- Haswell
- Broadwell
- Skylake
- Kabylake
Polly uses since several months a performance model for BLAS computations that
derives optimal cache and register tile sizes from cache and latency
information (based on ideas from "Analytical Modeling Is Enough for High-Performance BLIS", by Tze Meng Low published at TOMS 2016).
While bootstrapping this model, these target values have been kept in Polly.
However, as our implementation is now rather mature, it seems time to teach
LLVM itself about cache sizes.
Interestingly, L1 and L2 cache sizes are pretty constant across
micro-architectures, hence a set of architecture specific default values
seems like a good start. They can be expanded to more target specific values,
in case certain newer architectures require different values. For now a set
of Intel architectures are provided.
Just as a little teaser, for a simple gemm kernel this model allows us to
improve performance from 1.2s to 0.27s. For gemm kernels with less optimal
memory layouts even larger speedups can be reported.
Reviewers: Meinersbur, bollu, singam-sanjay, hfinkel, gareevroman, fhahn, sebpop, efriedma, asb
Reviewed By: fhahn, asb
Subscribers: lsaba, asb, pollydev, llvm-commits
Differential Revision: https://reviews.llvm.org/D37051
llvm-svn: 311647
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 6c73a68..eeced40 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -66,6 +66,57 @@
return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
}
+llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
+ TargetTransformInfo::CacheLevel Level) const {
+ switch (Level) {
+ case TargetTransformInfo::CacheLevel::L1D:
+ // - Penry
+ // - Nehalem
+ // - Westmere
+ // - Sandy Bridge
+ // - Ivy Bridge
+ // - Haswell
+ // - Broadwell
+ // - Skylake
+ // - Kabylake
+ return 32 * 1024; // 32 KByte
+ case TargetTransformInfo::CacheLevel::L2D:
+ // - Penry
+ // - Nehalem
+ // - Westmere
+ // - Sandy Bridge
+ // - Ivy Bridge
+ // - Haswell
+ // - Broadwell
+ // - Skylake
+ // - Kabylake
+ return 256 * 1024; // 256 KByte
+ }
+
+ llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
+}
+
+llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
+ TargetTransformInfo::CacheLevel Level) const {
+ // - Penry
+ // - Nehalem
+ // - Westmere
+ // - Sandy Bridge
+ // - Ivy Bridge
+ // - Haswell
+ // - Broadwell
+ // - Skylake
+ // - Kabylake
+ switch (Level) {
+ case TargetTransformInfo::CacheLevel::L1D:
+ LLVM_FALLTHROUGH;
+ case TargetTransformInfo::CacheLevel::L2D:
+ return 8;
+ }
+
+ llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
+}
+
unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
if (Vector && !ST->hasSSE1())
return 0;