[CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand
Currently, instructions doing memory accesses through a base operand that is
not a register can not be analyzed using `TII::getMemOpBaseRegImmOfs`.
This means that functions such as `TII::shouldClusterMemOps` will bail
out on instructions using an FI as a base instead of a register.
The goal of this patch is to refactor all this to return a base
operand instead of a base register.
Then in a separate patch, I will add FI support to the mem op clustering
in the MachineScheduler.
Differential Revision: https://reviews.llvm.org/D54846
llvm-svn: 347746
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index bb5fc66..de8c555 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1121,11 +1121,12 @@
// First, perform the cheaper check that compares the base register.
// If they are the same and the load offset is less than the store
// offset, then mark the dependence as loop carried potentially.
- unsigned BaseReg1, BaseReg2;
+ MachineOperand *BaseOp1, *BaseOp2;
int64_t Offset1, Offset2;
- if (TII->getMemOpBaseRegImmOfs(LdMI, BaseReg1, Offset1, TRI) &&
- TII->getMemOpBaseRegImmOfs(MI, BaseReg2, Offset2, TRI)) {
- if (BaseReg1 == BaseReg2 && (int)Offset1 < (int)Offset2) {
+ if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, TRI) &&
+ TII->getMemOperandWithOffset(MI, BaseOp2, Offset2, TRI)) {
+ if (BaseOp1->isIdenticalTo(*BaseOp2) &&
+ (int)Offset1 < (int)Offset2) {
assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI, AA) &&
"What happened to the chain edge?");
SDep Dep(Load, SDep::Barrier);
@@ -3246,11 +3247,16 @@
/// during each iteration. Set Delta to the amount of the change.
bool SwingSchedulerDAG::computeDelta(MachineInstr &MI, unsigned &Delta) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- unsigned BaseReg;
+ MachineOperand *BaseOp;
int64_t Offset;
- if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
return false;
+ if (!BaseOp->isReg())
+ return false;
+
+ unsigned BaseReg = BaseOp->getReg();
+
MachineRegisterInfo &MRI = MF.getRegInfo();
// Check if there is a Phi. If so, get the definition in the loop.
MachineInstr *BaseDef = MRI.getVRegDef(BaseReg);
@@ -3653,19 +3659,19 @@
if (!computeDelta(*SI, DeltaS) || !computeDelta(*DI, DeltaD))
return true;
- unsigned BaseRegS, BaseRegD;
+ MachineOperand *BaseOpS, *BaseOpD;
int64_t OffsetS, OffsetD;
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- if (!TII->getMemOpBaseRegImmOfs(*SI, BaseRegS, OffsetS, TRI) ||
- !TII->getMemOpBaseRegImmOfs(*DI, BaseRegD, OffsetD, TRI))
+ if (!TII->getMemOperandWithOffset(*SI, BaseOpS, OffsetS, TRI) ||
+ !TII->getMemOperandWithOffset(*DI, BaseOpD, OffsetD, TRI))
return true;
- if (BaseRegS != BaseRegD)
+ if (!BaseOpS->isIdenticalTo(*BaseOpD))
return true;
// Check that the base register is incremented by a constant value for each
// iteration.
- MachineInstr *Def = MRI.getVRegDef(BaseRegS);
+ MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
if (!Def || !Def->isPHI())
return true;
unsigned InitVal = 0;